A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell. A first region is in electrical contact with the floating body region. A second region is in electrical contact with the floating body region and is spaced apart from the first region. A gate is positioned between the first and second regions. A buried layer is provided beneath the floating body region. An insulating layer is configured to insulate the memory cell from adjacent memory cells in a first direction. A buried insulating layer is configured to insulate the memory cell from adjacent memory cells in a second direction perpendicular to the first direction.

A method includes forming a first semiconductor fin and a second semiconductor fin parallel to each other and protruding higher than top surfaces of isolation regions. The isolation regions include a portion between the first and the second semiconductor fins. The method further includes forming a gate stack crossing over the first and the second semiconductor fins, etching a portion of the gate stack to form an opening, wherein the portion of the isolation regions, the first semiconductor fin, and the second semiconductor fin are exposed to the opening, etching the first semiconductor fin, the second semiconductor fin, and the portion of the isolation regions to extend the opening into a bulk portion of a semiconductor substrate below the isolation regions, and filling the opening with a dielectric material to form a cut-fin isolation region.

This disclosure is directed to techniques for fabricating CMOS devices for SRAM cells with resistors formed along transistor well sidewall edges by self-aligned, angled implantation, which may enable more compact SRAM architecture with SEU mitigation, such as for space-based or other radiation-hardened applications. An example method includes implanting a dopant into a doped semiconductor well covered by a barrier, wherein the doped semiconductor well is disposed on a buried insulator and wherein the dopant is of opposite doping type to the doped semiconductor well, thereby forming a resistor on an edge of the doped semiconductor well, wherein the resistor has the opposite doping type. The method further includes forming a second insulator adjacent to the resistor, removing the barrier, and forming a gate layer on the doped semiconductor well, thereby forming a gate adjacent to the doped semiconductor well and the resistor.

Semiconductor device structures with substrate biasing, methods of forming a semiconductor device structure with substrate biasing, and methods of operating a semiconductor device structure with substrate biasing. A substrate contact is coupled to a portion of a bulk semiconductor substrate in a device region. The substrate contact is configured to be biased with a negative bias voltage. A field-effect transistor includes a semiconductor body in the device region of the bulk semiconductor substrate. The semiconductor body is electrically isolated from the portion of the bulk semiconductor substrate.

Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes to form volumes of oxide within a fin, such as a Si fin. In embodiments, this may be accomplished by applying a catalytic oxidant material on a side of a fin and then annealing to form a volume of oxide. In embodiments, this may be accomplished by using a plasma implant technique or a beam-line implant technique to introduce oxygen ions into an area of the fin and then annealing to form a volume of oxide. Processes described here may be used manufacture a transistor, a stacked transistor, or a three-dimensional (3-D) monolithic stacked transistor.

An integrated power semiconductor device, includes devices integrated on a single chip. The devices include a vertical high voltage device, a first high voltage pLDMOS device, a high voltage nLDMOS device, a second high voltage pLDMOS device, a low voltage NMOS device, a low voltage PMOS device, a low voltage NPN device, and a low voltage diode device. A dielectric isolation is applied to the first high voltage pLDMOS device, the high voltage nLDMOS device, the second high voltage pLDMOS device, the low voltage NMOS device, the low voltage PMOS device, the low voltage NPN device, and the low voltage diode device. A multi-channel design is applied to the first high voltage pLDMOS device, and the high voltage nLDMOS device. A single channel design is applied to the second high voltage pLDMOS device.

A method includes forming a first semiconductor fin and a second semiconductor fin parallel to each other and protruding higher than top surfaces of isolation regions. The isolation regions include a portion between the first and the second semiconductor fins. The method further includes forming a gate stack crossing over the first and the second semiconductor fins, etching a portion of the gate stack to form an opening, wherein the portion of the isolation regions, the first semiconductor fin, and the second semiconductor fin are exposed to the opening, etching the first semiconductor fin, the second semiconductor fin, and the portion of the isolation regions to extend the opening into a bulk portion of a semiconductor substrate below the isolation regions, and filling the opening with a dielectric material to form a cut-fin isolation region.

A semiconductor device, the device including: a first silicon layer including a first single crystal silicon layer; a first metal layer disposed over the first single crystal silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer; and a via disposed through the second level, where the via has a diameter of less than 450 nm, and where a typical thickness of the fifth metal layer is greater than a typical thickness of the third metal layer by at least 50%.

A semiconductor device includes: a semiconductor substrate; an epitaxial layer or layer stack on the semiconductor substrate; a plurality of transistor cells of a first type formed in a first region of the epitaxial layer or layer stack and electrically coupled in parallel to form a vertical power transistor; a plurality of transistor cells of a second type different than the first type and formed in a second region of the epitaxial layer or layer stack; and an isolation structure that laterally and vertically delimits the second region of the epitaxial layer or layer stack. Sidewalls and a bottom of the isolation structure include a dielectric material that electrically isolates the plurality of transistor cells of the second type from the plurality of transistor cells of the first type in the epitaxial layer or layer stack. Methods of producing the semiconductor device are also described.

Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.