A semiconductor device includes: a semiconductor substrate; an epitaxial layer or layer stack on the semiconductor substrate; a plurality of transistor cells of a first type formed in a first region of the epitaxial layer or layer stack and electrically coupled in parallel to form a vertical power transistor; a plurality of transistor cells of a second type different than the first type and formed in a second region of the epitaxial layer or layer stack; and an isolation structure that laterally and vertically delimits the second region of the epitaxial layer or layer stack. Sidewalls and a bottom of the isolation structure include a dielectric material that electrically isolates the plurality of transistor cells of the second type from the plurality of transistor cells of the first type in the epitaxial layer or layer stack. Methods of producing the semiconductor device are also described.

The present description concerns an integrated circuit chip including a semiconductor substrate and a radiofrequency component arranged inside and on top of an active region of the semiconductor substrate. The semiconductor substrate includes an amorphous buried layer in contact, by its upper surface, with a lower surface of the active region of the semiconductor substrate.

A method comprises forming a first set of one or more fins in a first region from an insulated substrate and a second set of one or more fins in a second region from the insulated substrate. The insulated substrate comprises a silicon substrate, and an insulator layer deposited on the silicon substrate. The first region comprises a first material layer and the second region comprises a second material layer.

A method comprises forming one or more fins in a first region on an insulated substrate. The method also comprises forming one or more fins formed in a second region on the insulated substrate. The insulated substrate comprising a silicon substrate, and an insulator layer deposited on the silicon substrate. The one or more fins in the first region comprising a first material layer deposited on the insulator layer. The one or more fins in the second region comprising a second material layer deposited on the insulator layer.

Semiconductor wafers and methods of fabricating the same are provided. An example semiconductor wafer has multiple die regions separated by a die spacing region and includes a wafer substrate, multiple dies disposed over the wafer substrate, and multiple buried sacrificial structures corresponding to the multiple dies. Each die is located in the corresponding die region and further includes a die substrate, an integrated circuit (IC) device disposed in the die substrate, and a multi-layer interconnect structure disposed on the IC device. The buried sacrificial structure is surrounding the die substrate and disposed between the die and the wafer substrate. The buried sacrificial structure further includes a bottom portion disposed in the die region and a side portion circumferentially connected to the bottom portion. The side portion is located in the die spacing region surrounding the corresponding die and disposed on the sidewall of the die substrate.

Methods and structures for mitigating back-gate effects in a radio frequency (RF) silicon-on-insulator (SOI) substrate, RF-SOI, are presented. According to one aspect, a first implant or junction is formed in a region of a trap-rich layer (TRL) of the RF-SOI that is located below a first circuit/device to protect. The first implant or junction is fully contained within the TRL. A planar surface area of the first implant and/or junction fully contains a projection of a planar surface area of the first circuit and/or device. The first implant or junction is biased via a through BOX contact (TBC) that penetrates the BOX layer at a shallow trench isolation region formed in the RF-SOI. According to another aspect, a second implant or junction is formed in a region of the TRL below a second circuit/device. The first and second implants or junctions are disjoint and separated by an undoped region of the TRL.

A device and method for integrated circuits with surrounding gate structures are disclosed. The device includes a semiconductor substrate and a fin structure on the semiconductor substrate. The fin structure is doped with a first conductivity type and includes a source region at one distal end and a drain region at the opposite distal end. The device further includes a gate structure overlying a channel region disposed between the source and drain regions of the fin structure. The fin structure has a rectangular cross-sectional bottom portion and an arched cross-sectional top portion. The arched cross-sectional top portion is semi-circular shaped and has a radius that is equal to or smaller than the height of the rectangular cross-sectional bottom portion. The source, drain, and the channel regions each are doped with dopants of the same polarity and the same concentration.

A method for fabricating a semiconductor device includes forming an opening in a first epitaxial lateral overgrowth region to expose a surface of the semiconductor substrate within the opening. The method further includes forming an insulation region at the exposed surface of the semiconductor substrate within the opening and filling the opening with a second semiconductor material to form a second epitaxial lateral overgrowth region using a lateral epitaxial growth process.

A method includes forming a first semiconductor fin and a second semiconductor fin parallel to each other and protruding higher than top surfaces of isolation regions. The isolation regions include a portion between the first and the second semiconductor fins. The method further includes forming a gate stack crossing over the first and the second semiconductor fins, etching a portion of the gate stack to form an opening, wherein the portion of the isolation regions, the first semiconductor fin, and the second semiconductor fin are exposed to the opening, etching the first semiconductor fin, the second semiconductor fin, and the portion of the isolation regions to extend the opening into a bulk portion of a semiconductor substrate below the isolation regions, and filling the opening with a dielectric material to form a cut-fin isolation region.

Structures and methods for better optimizing the performance of all the circuitry of an SOI IC. Embodiments include SOI IC having dual-thickness active areas, such that digital and non-RF analog circuitry may be fabricated on a relatively thin active layer while RF circuitry may be fabricated on a relatively thick active layer. Fabrication of RF circuitry on the relatively thick active layer allows for improvements to the R.sub.ON*C.sub.OFF figure of merit for the FET devices, and for optimizations not feasible for RF circuitry fabricated on a relatively thin active layer. Structures and methods for two-level shallow-trench isolation (STI) structures and electrical contacts are disclosed. Some embodiments may include a substrate contact extending from the substantially planar upper surface of a dielectric layer overlaying the thin and thick active areas to at least the BOX layer.