Patent classifications
H
ELECTRICITY
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H01
ELECTRIC ELEMENTS
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H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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21/00
Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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H01L21/70
Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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H01L21/71
Manufacture of specific parts of devices defined in group H01L21/70
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H01L21/76
Making of isolation regions between components
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H01L21/762
Dielectric regions; , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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H01L21/7624
using semiconductor on insulator [SOI] technology
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H01L21/76264
SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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H01L21/76267
Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
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H01L21/76267

Back-gate effect control via doping
12432991 · 2025-09-30 · ·

Methods and structures for mitigating back-gate effects in a radio frequency (RF) silicon-on-insulator (SOI) substrate, RF-SOI, are presented. According to one aspect, a first implant or junction is formed in a region of a trap-rich layer (TRL) of the RF-SOI that is located below a first circuit/device to protect. The first implant or junction is fully contained within the TRL. A planar surface area of the first implant and/or junction fully contains a projection of a planar surface area of the first circuit and/or device. The first implant or junction is biased via a through BOX contact (TBC) that penetrates the BOX layer at a shallow trench isolation region formed in the RF-SOI. According to another aspect, a second implant or junction is formed in a region of the TRL below a second circuit/device. The first and second implants or junctions are disjoint and separated by an undoped region of the TRL.

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
20250331254 · 2025-10-23 · ·

A method for manufacturing a semiconductor device includes forming an electrode on a structure body. The structure body includes a first insulating film, a second insulating film, and a semiconductor part. The electrode includes a first electrode part and a second electrode part. The first electrode part extends in a first direction and travers a region directly above the semiconductor part. The second electrode part extends from the first electrode part in a second direction. The method includes forming a first semiconductor part. The method includes forming a first mask on the structure body. The method includes forming a second semiconductor part in a portion of the first semiconductor part by using the first mask and the electrode as a mask to ion-implant an impurity. The method includes removing the first mask. The method includes forming a contact connected to the one part.

BACK-GATE EFFECT CONTROL VIA DOPING
20250393268 · 2025-12-25 ·

Methods and structures for mitigating back-gate effects in a radio frequency (RF) silicon-on-insulator (SOI) substrate, RF-SOI, are presented. According to one aspect, a first implant or junction is formed in a region of a trap-rich layer (TRL) of the RF-SOI that is located below a first circuit/device to protect. The first implant or junction is fully contained within the TRL. A planar surface area of the first implant and/or junction fully contains a projection of a planar surface area of the first circuit and/or device. The first implant or junction is biased via a through BOX contact (TBC) that penetrates the BOX layer at a shallow trench isolation region formed in the RF-SOI. According to another aspect, a second implant or junction is formed in a region of the TRL below a second circuit/device. The first and second implants or junctions are disjoint and separated by an undoped region of the TRL.