The disclosure provides a pattern collapse free wet clean process for fabricating semiconductor devices. By performing post reactive ion etching (RIE) using a fluorine-containing gas such as C.sub.2F.sub.6, followed by cleaning in a single wafer cleaner (SWC) with diluted hydrofluoric acid (HF) or in a solution of ammonia and HF, a substrate with multiple pattern collapse free high aspect ratio shallow trench isolation (STI) features can be obtained.

Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.

The invention relates to a silicon-based multifunction substrate. The silicon-based multifunction substrate comprises bulk silicon regions extending from a front surface to a back surface of the silicon-based multifunction substrate and at least one buried oxide layer laterally arranged between the bulk silicon regions. The buried oxide layer is covered by a structured silicon layer extending up to the front surface. The structured silicon layer comprises, laterally arranged between the bulk silicon regions, at least two silicon-on-insulator regions, herein SOI regions, with different thicknesses above the buried oxide layer. The SOI regions of the structured silicon layer are electrically insulated from each other by a respective first trench isolation extending from the front surface to the buried oxide layer.

A semiconductor device includes a semiconductor substrate, a body layer, a source region, a drift layer, a drain region, a gate insulating film, and a gate electrode. The semiconductor substrate has an active layer. An element region is included in the active layer and partitioned by a trench isolation portion. The body layer is disposed at a surface layer portion of the active layer. The source region is disposed at a surface layer portion of the body layer. The drift layer is disposed at the surface layer portion of the active layer. The drain region is disposed at a surface layer portion of the drift layer. The gate insulating film is disposed on a surface of the body layer. The gate electrode is disposed on the gate insulating film. One of the source region and the drain region being a high potential region is surrounded by the other one being a low potential region.

Embodiments relate to a semiconductor structure and a method for fabricating the same. The method includes: providing a substrate, a first trench being formed in the substrate; forming a protective layer in the first trench, the protective layer covering a side wall and a bottom of the first trench; etching the protective layer and the substrate at the bottom of the first trench to form second trenches; forming a passivation layer at a bottom of each of the second trenches; and etching a side wall of each of the second trenches to form a groove, and forming a dielectric layer in the groove. The method can eliminate a process of forming a bit line contact structure, thereby reducing resistance of a bit line and simplifying fabrication processes of the bit line.

Embodiments relate to a semiconductor structure and a method for fabricating the same. The method includes: providing a substrate, where a plurality of first trench initial structures are formed on the substrate, and the first trench initial structures extend along a first direction; and sequentially performing a thermal oxidation process and an oxide etching process on trench walls of the first trench initial structures to form first trenches whose trench widths satisfy a first preset dimension. The semiconductor structure and the method for fabricating the same can precisely control a trench width dimension of a trench, to form an isolation structure having a precise dimension in the trench, thereby effectively reducing parasitic capacitance and improving production yield and electrical properties of the semiconductor structure.

A semiconductor structure and a method for forming a semiconductor structure are provided. The method includes receiving a semiconductor substrate having a first region and a second region; forming a dielectric layer over the semiconductor substrate; removing portions of the dielectric layer to form a dielectric structure in the first region, wherein the dielectric structure includes a base structure and a plurality of first isolation structures over the base structure; forming a semiconductor layer covering the first region and the second region; removing a portion of the semiconductor layer to expose a top surface of the plurality of first isolation structures; and forming a plurality of second isolation structures in the second region.

Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip comprises a semiconductor substrate. A semiconductor layer is disposed over the semiconductor substrate. An insulating structure is buried between the semiconductor substrate and the semiconductor layer. The insulating structure has a first region and a second region. The insulating structure has a first thickness in the first region of the insulating structure, and the insulating structure has a second thickness different than the first thickness in the second region of the insulating structure.

Embodiments of the disclosure provide a method, including forming a shallow trench isolation (STI) in a substrate. The method further includes doping the substrate with a noble dopant, thereby forming a disordered crystallographic layer under the STI. The method also includes converting the disordered crystallographic layer to a doped buried polysilicon layer under the STI and a high resistivity (HR) polysilicon layer under the doped buried polysilicon layer. The method includes forming a pair of contacts operatively coupled in a spaced manner to the doped buried polysilicon layer.

Embodiments of the disclosure provide a bipolar transistor structure with a collector on a polycrystalline isolation layer. A polycrystalline isolation layer may be on a substrate, and a collector layer may be on the polycrystalline isolation layer. The collector layer has a first doping type and includes a polycrystalline semiconductor. A base layer is on the collector layer and has a second doping type opposite the first doping type. An emitter layer is on the base layer and has the first doping type. A material composition of the doped collector region is different from a material composition of the base layer.