An apparatus includes a first trench formed in a semiconductor layer. The first trench has a first width and a first depth. A second trench is formed in the semiconductor layer. The second trench has a second width and a second depth. The first width is wider than the second width. A buried dielectric layer is disposed between a bottom semiconductor surface of the semiconductor layer and a substrate. The buried dielectric layer contacts a first bottom surface of the first trench. A liner dielectric is formed on the first bottom surface and a first sidewall of the first trench. A first layer is formed on the liner dielectric. A second layer is formed on the first layer and extends to the substrate through an opening formed on the first bottom surface.

An electronic circuit including a semiconductor substrate having first and second opposite surfaces and electric insulation trenches. Each trench separates first and second portions of the substrate and includes electrically-insulating walls made of a first electrically-insulating material, extending from the first surface to the second surface, and a core made of a filling material, separated from the substrate by the walls. For at least one of the trenches, the trench walls include electrically-insulating portions made of the first electrically-insulating material protruding from the first or second surface outside of the substrate and/or the trench includes an electrically-insulating wall made of the first electrical-insulating material protruding from the first or second surface outside of the substrate and coupling the trench walls.

Methods for seam-less gapfill comprising sequentially depositing a film with a seam, reducing the height of the film to remove the seam and repeating until a seam-less film is formed. Some embodiments include optional film doping and film treatment (e.g., ion implantation and annealing).

Methods for seam-less gapfill comprising sequentially depositing a film with a seam, reducing the height of the film to remove the seam and repeating until a seam-less film is formed. Some embodiments include optional film doping and film treatment (e.g., ion implantation and annealing).

A semiconductor device has a semiconductor material in a substrate. The semiconductor device has an MOS transistor. A trench in the substrate extends from a top surface of the substrate) into the semiconductor material. A shield is disposed in the trench. The shield has a contact portion which extends toward a top surface of the trench. A gate of the MOS transistor is disposed in the trench over the shield. The gate is electrically isolated from the shield. The gate is electrically isolated from the contact portion of the shield by a shield isolation layer which covers an angled surface of the contact portion extending toward the top of the trench. Methods of forming the semiconductor device are disclosed.

An integrated circuit includes a semiconductor substrate with an electrically isolated semiconductor well. An upper trench isolation extends from a front face of the semiconductor well to a depth located a distance from the bottom of the well. Two additional isolating zones are electrically insulated from the semiconductor well and extending inside the semiconductor well in a first direction and vertically from the front face to the bottom of the semiconductor well. At least one hemmed resistive region is bounded by the two additional isolating zones, the upper trench isolation and the bottom of the semiconductor well. Electrical contacts are electrically coupled to the hemmed resistive region.

A semiconductor device includes a semiconductor substrate having a first region and a second region. The semiconductor device also includes an insulating structure laterally between the first region and the second region in the semiconductor substrate. The insulating structure electrically insulates the first region laterally from the second region in the semiconductor substrate. The semiconductor device further includes a connecting structure at a surface of the semiconductor substrate. The connecting structure contacts at least a sub-structure of the insulating structure and at least one of the first region and the second region. At least a sub-structure of the connecting structure has an electrical resistivity greater than 1*10.sup.3 m and less than 1*10.sup.12 m.

The present disclosure relates to isolation structures for semiconductor devices and, more particularly, to dual trench isolation structures having a deep trench and a shallow trench for electrically isolating integrated circuit (IC) components formed on a semiconductor substrate. The semiconductor isolation structure of the present disclosure includes a semiconductor substrate, a shallow trench isolation (STI) disposed over the semiconductor substrate, a deep trench isolation (DTI) with sidewalls extending from a bottom surface of the STI and terminating in the semiconductor substrate, a multilayer dielectric lining disposed on the sidewalls of the DTI, the multilayer dielectric lining including an etch stop layer positioned between inner and outer dielectric liners, and a filler material disposed within the DTI.

A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

An electronic circuit including a semiconductor substrate having first and second opposite surfaces and electrically-insulating trenches. Each trench includes at least first and second insulating portions made of a first insulating material, extending from the first surface to the second surface, first and second intermediate portions, extending from the first surface to the second surface, made of a first filling material, and a third insulating portion extending from the first surface to the second surface, the first insulating portion being in contact with the first intermediate portion, the second insulating portion being in contact with the second intermediate portion, and the third insulating portion being interposed between the intermediate portions.