A manufacturing method of a semiconductor device includes the following steps. First patterned structures are formed on a substrate. Each of the first patterned structures includes a first semiconductor pattern and a first bottom protection pattern disposed between the first semiconductor pattern and the substrate. A first protection layer is formed on the first patterned structures and the substrate. A part of the first protection layer is located between the first patterned structures. A first opening is formed in the first protection layer between the first patterned structures. The first opening penetrates the first protection layer and exposes a part of the substrate. A first etching process is performed after forming the first opening. A part of the substrate under the first patterned structures is removed by the first etching process for suspending at least a part of each of the first patterned structures above the substrate.

An electronic assembly, having a carrier wafer with a top wafer surface and a bottom wafer surface; an electronic integrated circuit being formed in the carrier wafer and comprising first and second integrated circuit contact pads; said carrier wafer comprising a through-wafer cavity having walls that join said top wafer surface to said bottom wafer surface; first and second component chips held in said through-wafer cavity each by direct contact of at least a side surface of said first and second component chips with a heat conducting attachment material that fills said through-wafer cavity; said first and second component chips comprising respectively at least a first and a second component contact pads; a barrier having a heat conductivity lower than a heat conductivity of said carrier wafer held by said heat conducting attachment material in said through-wafer cavity between said first and said second component chips.

The present disclosure relates to a method of making an electronic device comprising a first wafer including at least one trench and a second wafer, the second wafer being bonded, by hybrid bonding, to the first wafer, so as to form, at the level of the trench, at least one enclosed space, empty or gas-filled.

The present disclosure relates to semiconductor structures and, more particularly, to a wafer with localized cavity structures and methods of manufacture. A structure includes a bulk substrate with localized semiconductor on insulator (SOI) regions and bulk device regions, the localized SOI regions includes multiple cavity structures and substrate material of the bulk substrate.

RF electronic circuit comprising at least: a substrate comprising at least one support layer and a semiconducting surface layer located on the support layer; at least one electronic component able to carry out at least one of the RF signal transmission and/or reception and/or processing functions, and made in or on a first region of the surface layer; a matrix of cavities located in at least one first region of the support layer located under the first region of the surface layer, facing at least the electronic component, and such that the internal volumes of the cavities are separated and isolated from each other by portions of the support layer.

Disclosed are non-volatile memory devices and methods of manufacturing the same. The non-volatile memory device includes device isolation patterns defining active portions in a substrate and gate structures disposed on the substrate. The active portions are spaced apart from each other in a first direction and extend in a second direction perpendicular to the first direction. The gate structures are spaced apart from each other in the second direction and extend in the first direction. Each of the device isolation patterns includes a first air gap, and each of a top surface and a bottom surface of the first air gap has a wave-shape in a cross-sectional view taken along the second direction.

A Silicon on Insulator (SOI) structure and a method for creating an undercut (UCUT) in an SOI structure, in particular, for a 300 mm SOI platform, is provided. In particular, the method includes fabricating one or more cavities in a silicon substrate underneath an insulator layer of the SOI structure by performing a first dry etch of the silicon substrate to create the one or more cavities, performing a first wet etch of the silicon substrate to expand the one or more cavities, performing a second dry etch of the silicon substrate to further expand the one or more cavities and to break silicon facets created by the first wet etch, and performing a second wet etch to further expand the one or more cavities.

A semiconductor structure includes semiconductor layers disposed over a substrate and oriented lengthwise in a first direction, a metal gate stack disposed over the semiconductor layers and oriented lengthwise in a second direction perpendicular to the first direction, where the metal gate stack includes a top portion and a bottom portion that is interleaved with the semiconductor layers, source/drain features disposed in the semiconductor layers and adjacent to the metal gate stack, and an isolation structure protruding from the substrate, where the isolation structure is oriented lengthwise along the second direction and spaced from the metal gate stack along the first direction, and where the isolation structure includes a dielectric layer and an air gap.

Methods and devices for protecting against electrical discharges are provided. One such device for protecting against electrical discharges includes a semiconductor substrate and an isolation trench in the semiconductor substrate. The isolation trench includes an enclosed space that contains a gas.

Disclosed herein are integrated circuit (IC) components with substrate cavities, as well as related techniques and assemblies. In some embodiments, an IC component may include a substrate, a device layer on the substrate, a plurality of interconnect layers on the device layer, and a cavity in the substrate.