RF ELECTRONIC CIRCUIT COMPRISING CAVITIES BURIED UNDER RF ELECTRONIC COMPONENTS OF THE CIRCUIT

Abstract

RF electronic circuit comprising at least: a substrate comprising at least one support layer and a semiconducting surface layer located on the support layer; at least one electronic component able to carry out at least one of the RF signal transmission and/or reception and/or processing functions, and made in or on a first region of the surface layer; a matrix of cavities located in at least one first region of the support layer located under the first region of the surface layer, facing at least the electronic component, and such that the internal volumes of the cavities are separated and isolated from each other by portions of the support layer.

Claims

1. RF electronic circuit comprising at least: a substrate comprising at least one support layer and a semiconducting surface layer located on the support layer; at least one electronic component able to carry out at least one of the RF signal transmission and/or reception and/or processing functions, and made in or on a first region of the surface layer; a matrix of cavities located in at least one first region of the support layer located under the first region of the surface layer, facing at least the electronic component, and such that the internal volumes of the cavities are separated and isolated from each other by portions of the support layer, and in which one lateral dimension of each cavity is greater than or equal to about 10 μm.

2. RF electronic circuit according to claim 1, in which the substrate is of the semiconductor on insulator type and also comprises a buried dielectric layer located between the surface layer and the support layer.

3. RF electronic circuit according to claim 2, in which the cavities open up at a face of the buried dielectric layer such that said face of the buried dielectric layer forms a wall of each of the cavities.

4. RF electronic circuit according to claim 2, in which the thickness of a portion of the support layer between the buried dielectric layer and the cavities is between about 100 nm and 1 μm.

5. RF electronic circuit according to claim 2, in which the first region of the support layer extends between a first plane parallel to an interface between the support layer and the buried dielectric layer and a second plane different from the first plane and parallel to the interface between the support layer and the buried dielectric layer.

6. RF electronic circuit according to claim 5, in which a maximum lateral dimension of each of the cavities in each of the first and second planes is approximately equal to a distance separating two neighboring cavities and/or is between about 10 μm and 40 μm.

7. RF electronic circuit according to claim 5, in which the shape of the section of each of the cavities in each of the first and second planes is approximately circular or hexagonal.

8. RF electronic circuit according to claim 5, in which a maximum lateral dimension of each of the cavities in a third plane parallel to the first and second planes and located between the first and the second planes is greater than or equal to a maximum lateral dimension of each of the cavities in each of the first and second planes.

9. RF electronic circuit according to claim 8, in which the section through each of the cavities in the third plane is approximately circular or hexagonal.

10. RF electronic circuit according to claim 1, in which the thickness of the first region of the support layer is between about 1 μm and 10 μm.

11. RF electronic circuit according to claim 1, in which the cavities are extended in a second region of the support layer such that the first region of the support layer is located between the surface layer and the second region of the support layer.

12. RF electronic circuit according to claim 1, in which the cavities are hermetically closed.

13. RF electronic circuit according to claim 1, in which the cavities are filled with at least one of the following elements: air, a material with a relative dielectric permittivity of less than about 5, or a neutral gas.

14. Method of making an RF electronic circuit comprising at least the following steps: make at least one electronic component capable of implementing at least one of the RF signal transmission and/or reception and/or processing functions, in or on a first region of a semiconducting surface layer of a substrate also comprising at least one support layer on which the surface layer is located; make a matrix of cavities located in at least one first region of the support layer located under the first region of the surface layer, facing at least the electronic component, and such that the internal volumes of the cavities are separated and isolated from each other by portions of the support layer and such that a lateral dimension of each of the cavities is greater than or equal to about 10 μm.

15. Method according to claim 14, in which the step to make the cavities comprises the following steps: thinning of the support layer such that a remaining thickness of the support layer forms a layer with the same thickness as the first region of the support layer; etch cavities in the first region of the support layer; solidarize a second layer in contact with said layer with the same thickness as the first region of the support layer, this second layer closing the cavities on the side opposite the side on which the surface layer is located.

16. Method according to claim 14, in which the step to make the matrix of cavities includes etching of cavities through a first face of the support layer opposite a second face of the support layer on the same side as the surface layer, in the first region of the support layer and in a second region of the support layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0043] This invention will be better understood after reading the description of example embodiments given purely for information and that are in no way limitative with reference to the appended drawings on which:

[0044] FIG. 1 shows a diagrammatic sectional view of a first embodiment of an RF electronic circuit;

[0045] FIGS. 2 and 3 diagrammatically show sectional views of cavities made in the substrate of a first embodiment of an RF electronic circuit;

[0046] FIG. 4 shows a diagrammatic sectional view of a second embodiment of an RF electronic circuit;

[0047] Identical, similar or equivalent parts of the different figures described below have the same numeric references to facilitate comparison between the different figures.

[0048] The different parts shown on the figures are not necessarily all at the same scale, to make the figures more easily understandable.

[0049] It must be understood that the different possibilities (variants and embodiments) are not mutually exclusive and that they can be combined with each other.

DETAILED PRESENTATION OF PARTICULAR EMBODIMENTS

[0050] Refer firstly to FIG. 1 that shows a diagrammatic sectional view of a first embodiment of an RF electronic circuit 100.

[0051] The circuit 100 is made from a semiconductor on insulator type substrate, for example an SOI substrate. This SOI substrate includes for example a support layer or a solid layer 102, for example comprising a semiconductor and advantageously silicon, on which a buried dielectric or BOX layer 104 is arranged, for example comprising SiO.sub.2. A semiconducting surface layer 106, for example including silicon in this case, is arranged on the buried dielectric layer 104.

[0052] The thickness of the support layer 102 may for example be between about 500 μm and 775 μm, particularly when the SOI substrate corresponds to a wafer with a diameter equal to 300 mm, or more generally between about 150 μm and 775 μm. For example, the surface layer 106 may be between about 50 nm and 150 nm thick.

[0053] The circuit 100 comprises electronic components 107 made on/or in the surface layer 106, forming the Front-End (FEOL) part of the circuit 100.

[0054] The circuit 100 also comprises conducting and dielectric layers arranged alternately on the Front-End part of the circuit 100 and forming the Back-End of BEOL part 108 of the circuit 100. These conducting and dielectric layers form electrical connections within the circuit 100, between the electronic components 107, and one or several electrical accesses 110 to connect the circuit 100 to elements external to the circuit 100.

[0055] At least some of the components among all these electronic components 107 form an RF part of the circuit 100. These electronic components forming the RF part of the circuit 100 are capable in particular of implementing at least one RF signal transmission and/or reception and/or processing function, for example signal conversions between the base band and the RF frequencies band. These electronic components 107 forming the RF part of the circuit 100 correspond for example to LDMOS transistors, RF switches, inductances, etc. These electronic components of the RF part of the circuit 100 are made in and/or on a first region 112 of the surface layer 106.

[0056] The circuit 100 also comprises a matrix of cavities 114 located in a first region 116 of the support layer 102 located on the same side as the buried dielectric layer 104 (this first region 116 of the support layer 102 is in contact with the buried dielectric layer 104). The thickness of this first region 116 is H.sub.1, while the thickness of the remaining part of the support layer 102 is H.sub.2. If the total thickness of the support layer 102 is equal to for example about 200 μm, then H.sub.1+H.sub.2=200 μm.

[0057] The value of the thickness H.sub.1 is defined as a function of the required RF performances for the electronic components forming the RF part of the circuit 100 and that are located in and/or on the first region 112 of the surface layer 106. As the height of the cavities 114 increases (in this case equal to the thickness H.sub.1), the electrical insulation between the semiconductor of the support layer 12 and the electronic components 107 of the RF part of the circuit 100 improves. Advantageously, the thickness H.sub.1 is such that 1 μm≦H.sub.1≦μm.

[0058] In the first embodiment described with reference to FIG. 1, the cavities 114 are located entirely in the first region 116. Therefore a second region 118 of the support layer 102 located under this first region 116 comprises only the semiconductor of the support layer 102.

[0059] The first region 116 of the support layer 102 in which the cavities 114 are formed extends between a first plane parallel to an interface between the support layer 102 and the buried dielectric layer 104, referenced AA on FIG. 1, and a second plane also parallel to the interface between the support layer 102 and the buried dielectric layer 104, referenced BB on FIG. 1.

[0060] Plane AA is the plane in which the bottom walls of the cavities 114 are formed. This plane AA is located at the interface between the first region 116 of the support layer 102 and the second region 118 of the support layer 102.

[0061] Plane BB is the plane in which the top walls of the cavities 114 are formed. This plane BB is located at the interface between the buried dielectric region 104 and the support layer 102.

[0062] In the first embodiment, the cavities 114 open up at the bottom face of the buried dielectric layer 104 that forms the top walls of the cavities 114. Thus, the cavities 114 pass through the top face of the support layer 102.

[0063] Moreover, in this first embodiment, the cavities 114 are hermetically closed.

[0064] In the first embodiment described herein, the shape and the dimensions of the sections of the cavities 114 parallel to the principal plane of the SOI substrate (the principal plane of the SOI substrate is the horizontal plane parallel to the interface between the support layer 102 and the buried dielectric layer 104 or to the interface between the buried dielectric layer 104 and the surface layer 106 and that, on FIG. 1, corresponds to the (X,Y) plane) are not constant along the thickness H.sub.1 of the first region 116 of the support layer 102.

[0065] FIG. 2 shows a sectional view of the first region 116 of the support layer 102 in plane AA that corresponds to the plane parallel to the principal plane of the SOI substrate, passing in the support layer 102 and located at a distance equal to about H.sub.1 from the interface between the support layer 102 and the buried dielectric layer 104.

[0066] As shown on FIG. 2, the cavities 114 are laid out parallel to the principal plane of the SOI substrate, staggered from each other such that the cavities 114 are arranged one next to each other and forming a regular matrix of cavities 114. The cavities 114 in this case form a matrix in the principal plane of the SOI substrate, with width W and length L (corresponding to the dimensions of the first region 116 of the support layer 102), thus occupying an area similar to the area of the first region 112 in which the electronic components forming the RF part of the circuit 100 are made. Although the dimensions L and W are chosen as a function of the space occupied by the electronic components 107 of the RF part of the circuit 100, the length L is advantageously greater than or equal to about 100 μm and the width W is advantageously less than or equal to about 400 μm.

[0067] Moreover, in the first embodiment described herein, the section of each of the cavities in plane AA and in plane BB are approximately circular and their diameter is D. Furthermore, each cavity 114 in planes AA and BB is at a distance S from the adjacent cavities 114.

[0068] For example, the value of D is approximately the same as the value of S, which means that a lateral dimension or a maximum lateral dimension of each of the cavities 114 in the planes AA and BB is approximately equal to a distance separating two neighboring cavities. Furthermore, the value of D may for example be between about 10 μm and 40 μm.

[0069] FIG. 3 shows a sectional view of the first region 116 of the support layer 102 in plane CC that corresponds to the plane parallel to the principal plane of the SOI substrate and located at a distance equal to about H.sub.1/2 from each of the planes AA and BB. Therefore the plane CC corresponds to the plane passing at the mid-height of the cavities 114.

[0070] As already mentioned, the dimensions and shape of the section of the cavities 114 vary along their height. In the first embodiment described herein, the section in the plane CC of each of the cavities 114 is approximately hexagonal in shape with width E, in other words comprising six sides each with a length equal to E/2. The value of E in this case is such that D<E<(D+S).

[0071] The values of the dimensions D and E are chosen particularly as a function of the value of H.sub.1, such that for the entire matrix of cavities 114, a sufficient volume of the semiconductor of the support layer 102, even if it is slightly electrically conducting, is replaced by a medium that is a better electrical insulator than the semiconductor of the support layer 102. The cavities 114 are made such that they have good electrical insulation, in other words a high electrical resistance, and a low electrical capacitance. To achieve this, the internal volumes of the cavities 114 can be filled with air and/or a neutral gas. It is also possible that the internal volumes of the cavities 114 are filled with a material with low relative dielectric permittivity, for example less than about 5. For example, the cavities 114 can be filled with a polymer and/or an oxide, possibly porous.

[0072] The internal volumes of the cavities 114 are separated from and are isolated from each other by portions 120 of the first region 116 of the support layer 102, over the entire thickness H.sub.1 of the first region 116.

[0073] In the first embodiment described above, the cavities 114 open up on one face of the buried dielectric layer 104, in other words they pass through the face of the support layer 102 located on the same side as the buried dielectric layer 104. As a variant, it is possible that the cavities 114 do not pass through this face of the support layer 102 and therefore that a portion of the support layer 102 is located between the buried dielectric layer 104 and the matrix of cavities 114, or between the buried dielectric layer 104 and the first region 116 of the support layer 102. The thickness of this portion of the support layer 102 can be between about 100 μm and 1 μm.

[0074] To make the circuit 100 described above with reference to FIG. 1, the electronic components 107 are firstly made on and/or in the surface layer 106, thus forming the FEOL of the circuit 100. The BEOL 108 of the circuit 100 is then made.

[0075] The support layer 102 is then thinned from its back face so as to keep a semiconducting layer with a thickness equal to the thickness H.sub.1 of the first region 116. Before this thinning, when the remaining layer with the required thickness H.sub.1 does not give sufficient mechanical support, it is possible to firstly glue a temporary substrate, for example comprising glass, in contact with the front part of the circuit 100, in other words on the BEOL 108 of the circuit 100, so as to make it easier to manipulate the assembly while this thinning is being done and after thinning. Such a transfer of a temporary substrate can be judicious when the thickness of the support layer 102 is less than about 250 μm.

[0076] Lithography and etching steps are then applied to form the matrix of cavities 114 in the first region 116. Different shapes of cavities can be obtained depending on the etching method used and the required dimensions D, E and H.sub.1, for example as described in the documents entitled ‘Isotropic wet chemical etching of deep channels with optical surface quality in silicon with HNA based etching solutions” by M. Bauhuber et al., Materials Science in Semiconductor Processing 16, 2013, pages 1428-1433, and “Fabricating barbed microtip arrays by low-cost silicon wet etching techniques” by S.-W. Tung et al., IEEE Transducers 2013, Barcelona, Spain, Jun. 16-20, 2013, pages 1028-1031.

[0077] The method is completed by bonding (for example “direct bonding”) another semiconducting layer in contact with the layer in which the cavities 114 have been etched, so as to close the cavities 114. This bonding enables to make a support layer similar or close to the initial support layer (except the cavities 114). The temporary substrate is then removed to obtain a macroscopic configuration of the wafer similar to the initial configuration. Subsequent packaging steps can then be implemented.

[0078] As a variant to the first embodiment described above, the shapes of the different sections of the cavities 114 may be different from those described above. The dimensions may also be different from the dimensions described above. Moreover, the cavities 114 may be such that the section and/or the lateral dimensions of the cavities are approximately constant along the height of the cavities 114 (which for example means that the shape of the section of the cavities 114 and/or the lateral dimensions of the cavities can be similar in the planes AA, BB and CC).

[0079] FIG. 4 shows a diagrammatic view of the second embodiment of an RF electronic circuit 100.

[0080] Like the circuit 100 previously described with reference to FIGS. 1 to 3, the circuit 100 according to this second embodiment is made from an SOI substrate comprising the support layer 102, the buried dielectric layer 104 and the semiconducting surface layer 106. The circuit 100 also comprises the electronic components 107 (Front-End part), the BEOL 108, and the matrix of cavities 114 that, in the first region 116 of the support layer 102, are similar to those described above with reference to the first embodiment.

[0081] In this second embodiment, the cavities 114 are extended in the second region 118 of the support layer 102. In the example described herein, the extension of the cavities 114 is made throughout the thickness H.sub.2 of the second region 118. As a variant, it is possible that this extension of the cavities 114 is made only in part of the thickness H.sub.2 of the second region 118 (which implies that the semiconductor is present under these extension parts).

[0082] On FIG. 4, this extension of the cavities 114 forms cylindrical shaped parts 122, in other words each with a circular shaped section in the (X, Y) plane with diameter D, as for cavities 114 in plane AA.

[0083] Advantageously, the height H of these parts 122 depends on the value of D, particularly such that the value of the height H is equal to approximately 10*D.

[0084] As described above, the cavities 114 and the parts 122 can be empty, or they can be filled with air and/or a neutral gas. Advantageously, they can be covered entirely or on the side walls only, with a material that is a good thermal conductor (for example a metal such as Cu, W, etc.).

[0085] The step of bonding with the temporary substrate can be eliminated when making the circuit 100 according to this second embodiment.

[0086] The cavities 114 and the parts 122 are made with several etching steps. For example, in a first step, an anisotropic etching is implemented over the entire thickness H.sub.2 of the second region 118 of the support layer 102, thus forming the parts 122. For example, this first etching corresponds to a dry reactive ion etching like that used to etch TSVs.

[0087] A protection layer is then deposited for example corresponding to a PVD deposition of SiO.sub.2 over a thickness of about 200 nm, within the parts 122, on the lateral walls of these parts. The oxide thus deposited will also be etched at the bottom of the cavities 114 to enable the last etching step of the semiconductor forming the cavities 114. This is preferably done by an isotropic method so as to obtain parts of cavities 114 with hexagonal sections. It may be advantageous to make this isotropic etching using a liquid solution using a liquid solution combining the HF, HNO.sub.3, H.sub.2SO.sub.4 and H.sub.3PO.sub.4 elements that have good selectivity relative to SiO.sub.2, deposited on the side faces of the parts 122 and also of the buried dielectric layer 104. It will be noted that the latter chemistry can be dispensed either in the liquid phase or gas phase.

[0088] As a variant to the two embodiments described above, the shapes of the sections of the cavities 114 may be different from those described above, in other words different than circular or hexagonal. The dimensions may also be different from the dimensions described above. Moreover, the cavities 114 may be such that the section and/or the lateral dimensions of the cavities are approximately constant along the height of the cavities 114 (which for example means that the shape of the section of the cavities 114 and/or the lateral dimensions of the cavities can be similar in the planes AA, BB and CC), that can be obtained by anisotropic etching.

[0089] In all the embodiments, the shape and the volume of the cavities 122 are adjusted as a function of a compromise to be made between either minimising the volume of semiconductor between the cavities 122 and then giving priority to the electrical performances of the electronic parts 107 of the RF part of the circuit 100, or keeping a larger volume of semiconductor and giving priority to thermal performances, in other words to obtain a better resistance of components 107 at high power.

[0090] In the embodiments described above, the substrate corresponds to a semiconductor on insulator type substrate in which the support layer 102 comprises the semiconductor. As a variant, the support layer 102 may comprise at least one material that is not a semiconductor.

[0091] It is also possible that the substrate used is not a semiconductor on insulator type substrate. For example, it is possible that the semiconducting surface layer 106 is located directly on the support layer 102, without the presence of a buried dielectric layer between the surface layer 106 and the support layer 102. In this case, it is possible that the first region 116 of the support layer 102 in which the cavities 114 are made would be located in contact with the surface layer 106 if a part of the support layer 102 is not kept between the cavities 114 and the first region 112 of the surface layer 106.