Parasitic transistor formation under a semiconductor containing nanosheet device is eliminated by forming an airgap between the source/drain regions of the semiconductor containing nanosheet device and the semiconductor substrate. The airgap is created by forming a sacrificial germanium-containing semiconductor material at the bottom of the source/drain regions prior to the epitaxial growth of the source/drain regions from physically exposed sidewalls of each semiconductor channel material nanosheet of a nanosheet material stack. After inner dielectric spacer formation, the sacrificial germanium-containing semiconductor material can be reflown to seal any possible openings to the semiconductor substrate. The source/drain regions are then epitaxially grown and thereafter, the sacrificial germanium-containing semiconductor material is removed from the structure creating the airgap between the source/drain regions of the semiconductor containing nanosheet device and the semiconductor substrate.

A manufacturing method of a semiconductor device includes the following steps. First patterned structures are formed on a substrate. Each of the first patterned structures includes a first semiconductor pattern and a first bottom protection pattern disposed between the first semiconductor pattern and the substrate. A first protection layer is formed on the first patterned structures and the substrate. A part of the first protection layer is located between the first patterned structures. A first opening is formed in the first protection layer between the first patterned structures. The first opening penetrates the first protection layer and exposes a part of the substrate. A first etching process is performed after forming the first opening. A part of the substrate under the first patterned structures is removed by the first etching process for suspending at least a part of each of the first patterned structures above the substrate.

A manufacturing method of a semiconductor device includes the following steps. First patterned structures are formed on a substrate. Each of the first patterned structures includes a first semiconductor pattern and a first bottom protection pattern disposed between the first semiconductor pattern and the substrate. A first protection layer is formed on the first patterned structures and the substrate. A part of the first protection layer is located between the first patterned structures. A first opening is formed in the first protection layer between the first patterned structures. The first opening penetrates the first protection layer and exposes a part of the substrate. A first etching process is performed after forming the first opening. A part of the substrate under the first patterned structures is removed by the first etching process for suspending at least a part of each of the first patterned structures above the substrate.

A semiconductor-on-insulator (SOI) device including a handle wafer, a buried oxide (BOX), and a top device layer is provided. A plurality of elongated trenches are formed in the handle wafer. Air gaps are formed in the elongated trenches by pinching off each of the elongated trenches. In one approach, prior to the pinching off, a plurality of lateral openings are formed contiguous with the elongated trenches and adjacent to the BOX. The elongated trenches and/or the lateral openings reduce parasitic capacitance between the handle wafer and the top device layer. In another approach, sidewalls of the elongated trenches are implant-damaged so as to further reduce the parasitic capacitance between the handle wafer and the top device layer.

A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, and a conductive plug. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductive plug is electrically connected to the source drain structure while leaving a gap between the conductive plug and the spacer.

A semiconductor device may include a Silicon on Insulator (SOI) substrate, and a diode formed on the SOI substrate, the diode including a cathode region and an anode region. The semiconductor device may include at least one breakdown voltage trench disposed at an edge of the cathode region, and between the cathode region and the anode region.

A method includes a patterned hard mask layer formed over a substrate. The substrate is etched using the patterned hard mask layer to form a trench therein but leaving at least one elongated portion of the substrate inside the trench. A first isolation layer is formed over the patterned hard mask layer. The first isolation layer fills the trench and covers the at least one elongated portion of the substrate. A portion of the first isolation layer is removed to expose the at least one elongated portion of the substrate. The at least one elongated portion of the substrate is thereafter removed to form a first opening. A second isolation layer is formed over the first opening, the patterned hard mask layer, and the first isolation layer, the second isolation layer sealing the first opening to form an air gap.

A semiconductor structure and a method for manufacturing the same are disclosed. The semiconductor structure includes a semiconductor substrate, a multi-layer stack, a switch device, and an air void. The multi-layer stack is buried in the semiconductor substrate. The multi-layer stack includes a first filling layer and a second filling layer under the first filling layer, the first filling layer has a first etching rate, the second filling layer has a second etching rate, and the first etching rate and the second etching rate are different. The switch device is disposed over the semiconductor substrate. The air void is formed in the multi-layer stack and under the switch device. The air void is surrounded by dielectric filling material.

A method for manufacturing a semiconductor device, the method may include forming a first part of a hollow in first part of a first layer of the semiconductor device and coating a sidewall of the first part of the hollow with an etch stop material, wherein the forming of the first part of the hollow comprises performing at least one iteration of (i) anisotropic etching and (ii) deposition of the etch stop material; wherein when completed, the semiconductor device comprises a radio frequency (RF) circuit; forming a second part of the hollow in a second part of the first layer by performing isotropic etching that involves directing plasma through the first part of the hollow; wherein the second part of the hollow reaches either (a) a bottom of a second layer of the semiconductor device or (b) the RF circuit; and wherein at least a majority of the second part of the hollow is wider than at least a majority of the first part of the hollow.

The present disclosure relates to an air-cavity module having a thinned semiconductor die and a mold compound. The thinned semiconductor die includes a back-end-of-line (BEOL) layer, an epitaxial layer over the BEOL layer, and a buried oxide (BOX) layer with discrete holes over the epitaxial layer. The epitaxial layer includes an air-cavity, a first device section, and a second device section. Herein, the air-cavity is in between the first device section and the second device section and directly in connection with each discrete hole in the BOX layer. The mold compound resides directly over at least a portion of the BOX layer, within which the discrete holes are located. The mold compound does not enter into the air-cavity through the discrete holes.