A method for manufacturing a semiconductor device includes forming a first insulating film over a semiconductor substrate and forming a second insulating film on the first insulating film. The first insulating film is a tensile film having a first tensile stress and the second insulating film is either a tensile film having a second tensile stress that is less than the first tensile stress or a compressive film. The first insulating film and second insulating film are formed of a same material. A metal hard mask layer is formed on the second insulating film.

A semiconductor device includes a semiconductor substrate, a source/drain region, a source/drain contact and a conductive via and a first polymer layer. The source/drain region is in the semiconductor substrate. The source/drain contact is over the source/drain region. The conductive via is over the source/drain contact. From a top view, the conductive via has two opposite long sides and two opposite short sides connecting the long sides, and the short sides are shorter than the long sides and more curved than the long sides.

It is to provide a manufacturing method of a semiconductor device including the following steps of: preparing a semiconductor substrate having a silicon nitride film on the rear surface; forming an interlayer insulating film having a via hole on the main surface of the semiconductor substrate; and forming a via-fill selectively within the via hole. The method further includes the steps of: performing the wafer rear surface cleaning to expose the surface of the silicon nitride film formed on the rear surface of the semiconductor substrate; and thereafter, forming a photoresist film made of chemical amplification type resist on the interlayer insulating film and the via-fill over the main surface of the semiconductor substrate, in which the semiconductor substrate is stored in an atmosphere with the ammonium ion concentration of 1000 μg/m.sup.3 and less.

A semiconductor structure includes a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin, a first epitaxial source/drain (S/D) feature disposed over the first semiconductor fin, a second epitaxial S/D feature disposed over the second semiconductor fin, an interlayer dielectric (ILD) layer disposed over the first and the second epitaxial S/D features, and an S/D contact disposed over and contacting the first epitaxial S/D feature, where a portion of the S/D contact laterally extends over the second epitaxial S/D feature, and the portion is separated from the second epitaxial S/D feature by the ILD layer.

For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

A method includes forming a gate structure over a substrate. A dielectric cap is formed over the gate structure. An etch stop layer is deposited over the dielectric cap. An interlayer dielectric (ILD) layer is deposited over the etch stop layer. The ILD layer is in contact with a sidewall of the etch stop layer. A gate via in the ILD layer is formed to pass through the etch stop layer and the dielectric cap to the gate structure.

A semiconductor structure that includes: a semiconductor substrate having a semiconductor base and back end of the line (BEOL) wiring layers; a dielectric cap layer on the semiconductor base; trenches on the dielectric cap layer, each of the trenches including dielectric walls, a dielectric bottom in contact with the dielectric cap layer and a metal filling a space between the dielectric walls; air gap openings on the dielectric cap layer and interspersed with the trenches, each air gap opening between the dielectric wall from one metal trench and adjacent to the dielectric wall of a second metal, the dielectric cap layer forming a bottom of the air gap openings; and a second dielectric cap layer formed over the trenches and over the air gap openings, the second dielectric cap layer pinching off each air gap opening.

A finFET device and a method of forming are provided. The method includes forming a first dielectric layer over a transistor. The method also includes forming a second dielectric layer over the first dielectric layer. The method also includes forming a first opening in the second dielectric layer to expose at least a portion of a gate electrode of the transistor. The method also includes forming a second opening in the first dielectric layer to expose at least a portion of a source/drain region of the transistor. The second opening is connected to the first opening, and the first opening is formed before the second opening. The method also includes forming an electrical connector in the first opening and the second opening.

An electrical communication structure that includes a plurality of metal line levels, a first metal line in a first metal line level of the plurality of line levels, and a second metal line in an upper metal line level of the plurality of line levels. A base of the second metal line is atop a metal etch stop layer that is aligned with edges of the second metal line. The electrical communication structure further includes a via that extends from the first metal line to the second metal line through the plurality of line levels. the via is not in electrical communication with at least one an intermediate metal line within the plurality of line levels between the first metal line level and the upper metal line level. The via has a metal fill that is in direct contact with a metal fill of the first metal line.

A method for manufacturing semiconductor devices include steps of depositing a first photoresist over a first dielectric layer, first exposing the first photoresist to a first light-exposure using a first lithographic mask, and second exposing the first photoresist to a second light-exposure using a second lithographic mask. An overlap region of the first photoresist is exposed to both the first light-exposure and the second light-exposure. The first dielectric layer is thereafter patterned to form a mask overlay alignment mark in the overlap region. The patterning includes etching the first dielectric layer form a trench, and filling the trench with a conductive material to produce the alignment mark. A second dielectric layer is deposited over the alignment mark, and a second photoresist is deposited over the second dielectric layer. A third lithographic mask is aligned to the second photoresist using the underlying mask overlay alignment mark for registration.