Interconnect structures and methods and apparatuses for forming the same are disclosed. In an embodiment, a method includes supplying a process gas to a process chamber; igniting the process gas into a plasma in the process chamber; reducing a pressure of the process chamber to less than 0.3 mTorr; and after reducing the pressure of the process chamber, depositing a conductive layer on a substrate in the process chamber.

The present disclosure relates an integrated chip. The integrated chip includes a first interconnect disposed within an inter-level dielectric (ILD) structure over a substrate. A barrier layer is disposed along sidewalls of the ILD structure. The barrier layer has sidewalls defining an opening over the first interconnect. A second interconnect is disposed on the barrier layer. The second interconnect extends through the opening in the barrier layer and to the first interconnect.

Semiconductor device layout designs for Vt tuning are provided. In one aspect, a semiconductor device is provided. The semiconductor device includes: at least one first metal line in contact with a source or drain of an FET; at least one second metal line in contact with a gate of the FET, wherein the first metal line crosses the second metal line; and an oxygen diffusion blocking layer on top of the at least one first metal line in an overlap area of the at least one first metal line and the at least one second metal line. A method of forming a semiconductor device is also provided.

The present disclosure provides a method of manufacturing a semiconductor device and a semiconductor device. The method of manufacturing a semiconductor device includes: providing a substrate with trenches, and the trenches extending along a thickness direction of the substrate from a first surface of the substrate; forming a first auxiliary layer and a first conductive layer successively in the trenches, and the first conductive layer covering the first auxiliary layer; thinning the substrate on a second surface of the substrate to expose the first auxiliary layer; removing the first auxiliary layer to form first openings; forming a second medium layer on the second surface of the substrate; patterning the second medium layer to form second openings in the second medium layer, and the second openings exposing the first openings; and depositing a second initial conductive layer, the second initial conductive layer filling the first openings and the second openings.

A semiconductor device manufacturing method includes: providing a semiconductor base; patterning the first medium layer to form a groove extending along the base in the base; forming a first auxiliary layer and a first metal layer sequentially in the groove, where the first metal layer is located on the side of the first auxiliary layer towards the first medium layer; thinning the base on the second surface of the base to expose the first auxiliary layer; removing the first auxiliary layer to form a first opening; and forming a second metal layer on the second surface of the base, where the second metal layer fills the first opening.

Interconnect structures on a substrate have low resistivity and high dopant interfaces. In some embodiments, the structures may have an opening with a sidewall from an upper surface to an underlying metallic layer of copper, a barrier layer of tantalum nitride formed on the sidewall of the opening, a liner layer of cobalt or ruthenium formed on the barrier layer and on the underlying metallic layer, a first copper layer with a dopant with a first dopant content formed on the liner layer and filling a lower portion of the opening to form a via-the first dopant content is approximately 0.5 percent to approximately 10 percent, and a second copper layer with the dopant with a second dopant content formed on the first copper layer and filling the at least one opening—the second dopant content is more than zero to approximately 0.5 percent of the dopant and is less than the first dopant content.

Methods for forming interconnects on a substrate with low resistivity and high dopant interfaces. In some embodiments, a method includes depositing a first copper layer with a dopant with a first dopant content of 0.5 percent to 10 percent in the interconnect by sputtering a first copper-based target at a first temperature of zero degrees Celsius to 200 degrees Celsius, annealing the substrate at a second temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the first copper layer, depositing a second copper layer with the dopant with a second dopant content of zero percent to 0.5 percent by sputtering a second copper-based target at the first temperature of zero degrees Celsius to 200 degrees Celsius, and annealing the substrate at a third temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the second copper layer.

A semiconductor component includes a substrate having an opening. The semiconductor component further includes a first dielectric liner in the opening, wherein the first dielectric liner having a thickness T.sub.1 at a first end of the opening, and a thickness T.sub.2 at a second end of the opening, and R.sub.1 is a ratio of T.sub.1 to T.sub.2. The semiconductor component further includes a second dielectric liner over the first dielectric liner, wherein the second dielectric liner having a thickness T.sub.3 at the first end of the opening, a thickness T.sub.4 at the second end of the opening, R.sub.2 is a ratio of T.sub.3 to T.sub.4, and R.sub.1 is greater than R.sub.2.

Devices and methods that include for configuring a profile of a liner layer before filling an opening disposed over a semiconductor substrate. The liner layer has a first thickness at the bottom of the opening and a second thickness a top of the opening, the second thickness being smaller that the first thickness. In an embodiment, the filled opening provides a contact structure.

A MOSFET includes a semiconductor body having a first side, a drift region, a body region forming a first pn-junction with the drift region, a source region forming a second pn-junction with the body region, in a vertical cross-section, a dielectric structure on the first side and having an upper side; a first gate electrode, a second gate electrode, a contact trench between the first and second gate electrodes, extending through the dielectric structure to the source region, in a horizontal direction a width of the contact trench has, in a first plane, a first value, and, in a second plane, a second value which is at most about 2.5 times the first value, and a first contact structure arranged on the dielectric structure having a through contact portion arranged in the contact trench, and in Ohmic contact with the source region.