Interconnect structures and methods and apparatuses for forming the same are disclosed. In an embodiment, a method includes supplying a process gas to a process chamber; igniting the process gas into a plasma in the process chamber; reducing a pressure of the process chamber to less than 0.3 mTorr; and after reducing the pressure of the process chamber, depositing a conductive layer on a substrate in the process chamber.

A nitrogen plasma treatment is used on an adhesion layer of a contact plug. As a result of the nitrogen plasma treatment, nitrogen is incorporated into the adhesion layer. When a contact plug is deposited in the opening, an interlayer of a metal nitride is formed between the contact plug and the adhesion layer. A nitrogen plasma treatment is used on an opening in an insulating layer. As a result of the nitrogen plasma treatment, nitrogen is incorporated into the insulating layer at the opening. When a contact plug is deposited in the opening, an interlayer of a metal nitride is formed between the contact plug and the insulating layer.

A method for CMP includes following operations. A dielectric structure is received. The dielectric structure includes a metal layer stack formed therein. The metal layer stack includes at least a first metal layer and a second metal layer, and the first metal layer and the second metal layer are exposed through a surface of the dielectric structure. A first composition is provided to remove a portion of the first metal layer from the surface of the dielectric structure. A second composition is provided to form a protecting layer over the second metal layer. The protecting layer is removed from the second metal layer. A CMP operation is performed to remove a portion of the second metal layer. In some embodiments, the protecting layer protects the second metal layer during the removal of the portion of the first metal layer.

A semiconductor device is provided. The semiconductor device includes a dielectric layer over a substrate and a contact structure embedded in the dielectric layer. The contact structure includes a diffusion barrier contacting the dielectric layer, the diffusion barrier including a titanium (Ti)-containing alloy. The contact structure further includes a liner on the diffusion barrier, the liner including a noble metal. The contact structure further includes a conductive plug on the liner.

A device includes a substrate, a gate structure wrapping around a vertical stack of nanostructure semiconductor channels, and a source/drain abutting the vertical stack and in contact with the nanostructure semiconductor channels. The device includes a gate via in contact with the first gate structure. The gate via includes a metal liner layer having a first flowability, and a metal fill layer having a second flowability higher than the first flowability.

A method includes forming an insulating layer over a conductive feature; etching the insulating layer to expose a first surface of the conductive feature; covering the first surface of the conductive feature with a sacrificial material, wherein the sidewalls of the insulating layer are free of the sacrificial material; covering the sidewalls of the insulating layer with a barrier material, wherein the first surface of the conductive feature is free of the barrier material, wherein the barrier material includes tantalum nitride (TaN) doped with a transition metal; removing the sacrificial material; and covering the barrier material and the first surface of the conductive feature with a conductive material.

Metal nitride diffusion barriers may be included between cobalt-based structures and ruthenium-based structures to reduce, minimize, and/or prevent intermixing of cobalt into ruthenium. A metal nitride diffusion barrier layer may include a cobalt nitride (CoN.sub.x), a ruthenium nitride (RuN.sub.x), or another metal nitride that has a bond dissociation energy greater than the bond dissociation energy of cobalt to cobalt (Co—Co), and may therefore function as a strong barrier to cobalt migration and diffusion into ruthenium. Moreover, cobalt nitride and ruthenium nitride have lower resistivity relative to other materials such as titanium nitride (TiN), tungsten nitride (WN), and tantalum nitride (TaN). In this way, the metal nitride diffusion barriers are capable of minimizing cobalt diffusion and intermixing into ruthenium-based interconnect structures while maintaining a low contact resistance for the interconnect structures. This may increase semiconductor device performance, may increase semiconductor device yield, and may enable further reductions in interconnect structure size.

Described are microelectronic devices comprising a dielectric layer formed on a substrate, a feature comprising a gap defined in the dielectric layer, a barrier layer on the dielectric layer, a two metal liner film on the barrier layer and a gap fill metal on the two metal liner. Embodiments provide a method of forming a microelectronic device comprising the two metal liner film on the barrier layer.

The present disclosure relates to a semiconductor device and a method for forming a semiconductor device with a graphene conductive structure. The semiconductor device includes a first gate structure disposed over a semiconductor substrate, and a first source/drain region disposed in the semiconductor substrate and adjacent to the first gate structure. The semiconductor device also includes a first silicide layer disposed in the semiconductor substrate and over the first source/drain region, and a graphene conductive structure disposed over the first silicide layer. The semiconductor device further includes a first dielectric layer covering the first gate structure, and a second dielectric layer disposed over the first dielectric layer. The graphene conductive structure is surrounded by the first dielectric layer and the second dielectric layer.

Semiconductor devices includes a first interlayer insulating layer, a lower interconnection line in the first interlayer insulating layer, an etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on the etch stop layer, and an upper interconnection line in the second interlayer insulating layer. The upper interconnection line includes a via portion extending through the etch stop layer and contacting the lower interconnection line. The via portion includes a barrier pattern and a conductive pattern. The barrier pattern includes a first barrier layer between the conductive pattern and the second interlayer insulating layer, and a second barrier layer between the conductive pattern and the lower interconnection line. A resistivity of the first barrier layer is greater than that of the second barrier layer. A nitrogen concentration of the first barrier layer is greater than that of the second barrier layer.