A method includes forming a first metallic feature, forming a dielectric layer over the first metallic feature, etching the dielectric layer to form an opening, with a top surface of the first metallic feature being exposed through the opening, and performing a first treatment on the top surface of the first metallic feature. The first treatment is performed through the opening, and the first treatment is performed using a first process gas. After the first treatment, a second treatment is performed through the opening, and the second treatment is performed using a second process gas different from the first process gas. A second metallic feature is deposited in the opening.

A semiconductor device includes a first dielectric layer over a device base layer, the first dielectric layer having a first opening with a first sidewall; a first interconnect segment extending through the first opening; and a cap layer over a top surface of the first interconnect segment, wherein the cap layer comprises a first metal, carbon, and nitrogen.

A semiconductor structure includes at least one first semiconductor device located on a substrate, lower-level dielectric material layers embedding lower-level metal interconnect structures, at least one second semiconductor device and a dielectric material portion that overlie the lower-level dielectric material layers, at least one upper-level dielectric material layer, and an interconnection via structure vertically extending from the at least one upper-level dielectric material layer to a conductive structure that can be a node of the at least one first semiconductor device or one of lower-level metal interconnect structures. The interconnection via structure includes a transition metal layer and a fluorine-doped filler material portion in contact with the transition metal layer, composed primarily of a filler material selected from a silicide of the transition metal element or aluminum oxide, and including fluorine atoms.

Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.

An integrated circuit product includes a first layer of insulating material including a first insulating material. The first layer of insulating material is positioned above a device layer of a semiconductor substrate. The first layer of insulating material has a lowermost surface positioned above an uppermost surface of a gate of a transistor in a device layer of a semiconductor substrate. The device layer includes transistors. A metallization blocking structure is positioned in an opening in the first layer of insulating material. The metallization blocking structure has a lowermost surface above the uppermost surface of the gate and includes a second insulating material that is different from the first insulating material. The metallization blocking structure includes a second insulating material that is different from the first insulating material. A metallization trench is defined in the first layer of insulating material on opposite sides of the metallization blocking structure. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure. The conductive metallization line has a long axis extending along the first and second portions.

Processing methods comprise forming a gap fill layer comprising tungsten or molybdenum by exposing a substrate surface having at least one feature thereon sequentially to a metal precursor and a reducing agent comprising hydrogen to form the gap fill layer in the feature, wherein there is not a nucleation layer between the substrate surface and the gap fill layer.

There is provided a semiconductor device including a first conductive layer formed on a substrate; a second conductive layer serving as a wiring layer and a barrier layer provided between the first conductive layer and the second conductive layer, wherein the barrier layer is made of a graphene film, and the second conductive layer includes a metal silicide compound, the metal silicide compound being provided so as to be in contact with the graphene film constituting the barrier layer.

An integrated circuit product includes a first layer of insulating material above a device layer of a semiconductor substrate and with a lowermost surface above an uppermost surface of a gate of a transistor in a device layer of the semiconductor substrate. A metallization blocking structure is in an opening in the first layer of insulating material and has a lowermost surface above the uppermost surface of the gate and includes a second insulating material that is different from the first insulating material. A metallization trench is in the first layer of insulating material on opposite sides of the metallization blocking structure. A contact structure is in the second insulating material and entirely below the metallization trench. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure and a long axis extending along the first and second portions.

Some embodiments include a method of forming an integrated assembly. An arrangement is formed to include a conductive pillar extending through an insulative mass. An upper surface of the conductive pillar is recessed to form a cavity. An insulative collar is formed within the cavity to line an outer lateral periphery of the cavity. A recessed surface of the conductive pillar is exposed at a bottom of the lined cavity. A conductive expanse is formed over the insulative mass. A portion of the conductive expanse extends into the cavity and is configured as an interconnect. The conductive expanse is patterned into multiple conductive structures. One of the conductive structures includes the interconnect.

The present application discloses method for fabricating a conductive feature and a method for fabricating a semiconductor device. The method includes providing a substrate; forming a recess in the substrate; conformally forming a first nucleation layer in the recess; performing a post-treatment to the first nucleation layer; and forming a first bulk layer on the first nucleation layer to fill the recess. The first nucleation layer and the first bulk layer configure the conductive feature. The first nucleation layer and the first bulk layer include tungsten. The post-treatment includes a borane-containing reducing agent.