A wetting tool that provides improved wettability and debris removal from features defined by a patterned resist layer on a substrate. The substrate wetting tool relies on a wetting solution having a pH of 2.0 or less and/or a temperature ranging from 20 to 50 C. With a pH of 2.0 or less, the resist material used to form features chemically reacts, making it more hydrophilic. The wetting solution is therefore attracted into the features, beneficially reducing the chance of bubble formation and removing debris. At elevated temperatures, the heated wetting solution improves particle de-lamination and aids in dissolving debris and oxides from the substrate surface.

According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a silicon carbide semiconductor body and a metal adhesion and barrier structure between the metal structure and the silicon carbide semiconductor body. The metal adhesion and barrier structure includes a layer comprising titanium and tungsten.

Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.

Provided are deposition processes including deposition of a thin, protective Mo layer using a molybdenum chloride (MoCl.sub.x) precursor. This may be followed by Mo deposition to fill the feature using a molybdenum oxyhalide (MoO.sub.yX.sub.z) precursor. The protective Mo layer enables Mo fill using an MoO.sub.yX.sub.z precursor without oxidation of the underlying surfaces. Also provided are in-situ clean processes in which a MoCl.sub.x precursor is used to remove oxidation from underlying surfaces prior to deposition. Subsequent deposition using the MoCl.sub.x precursor may deposit an initial layer and/or fill a feature.

Semiconductor device is provided. The semiconductor device includes a base substrate having a PMOS region and an NMOS region; a plurality gate structures formed on the base substrate, the gate structures including an interface layer formed on the base substrate, a high-K gate dielectric layer formed on the interface layer, a cap layer formed on the high-K gate dielectric layer and a metal layer formed over the high-K gate dielectric layer; an interlayer dielectric layer covering side surfaces of the gate structures formed over the base substrate; and source/drain doping regions formed in the base substrate at two sides of the gate structures. The gate structure is formed in an opening in the interlayer dielectric layer. The high-K gate dielectric layer is formed on side and bottom surfaces of the opening. The high-K dielectric layer contains additional oxygen ions diffused therein at a bottom portion.

Processing methods comprise forming a gap fill layer comprising tungsten or molybdenum by exposing a substrate surface having at least one feature thereon sequentially to a metal precursor and a reducing agent comprising hydrogen to form the gap fill layer in the feature, wherein there is not a nucleation layer between the substrate surface and the gap fill layer.

A method comprises depositing a barrier layer on a dielectric layer to prevent oxidation of a metal layer to be deposited by electroplating due to an oxide present in the dielectric layer and depositing a doped liner layer on the barrier layer to bond with the metal layer to be deposited on the liner layer by the electroplating. The dopant forms a protective passivation layer on a surface of the liner layer and dissolves during the electroplating so that the metal layer deposited on the liner layer by the electroplating bonds with the liner layer. The dopant reacts with the dielectric layer and forms a layer of a compound between the barrier layer and the dielectric layer. The compound layer prevents oxidation of the barrier layer and the liner layer due to the oxide present in the dielectric layer and adheres the barrier layer to the dielectric layer.

According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a semiconductor body and a metal adhesion and barrier structure between the metal structure and the semiconductor body. The metal adhesion and barrier structure includes a first layer having titanium and tungsten, and a second layer having titanium, tungsten, and nitrogen on the first layer having titanium and tungsten.

In one example, an electroplating system comprises a bath reservoir, a holding device, an anode, a direct current power supply, and a controller. The bath reservoir contains an electrolyte solution. The holding device holds a wafer submerged in the electrolyte solution. The wafer comprises features covered by a cobalt layer. The anode is opposite to the wafer and submerged in the electrolyte solution. The direct current power supply generates a direct current between the holding device and the anode. A combination of forward and reverse pulses is applied between the holding device and the anode to electroplate a copper layer on the cobalt layer of the wafer.

Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes forming an interlayer dielectric layer on a base substrate; forming a plurality of first openings and second openings in the interlayer dielectric layer, one first opening connecting to a second opening, the one first opening being between the second opening and the base substrate; forming a high-K gate dielectric layer on side and bottom surfaces of the first openings and on side surfaces of the second openings; forming a cap layer, containing oxygen ions, on the high-K gate dielectric layer; forming an amorphous silicon layer on the cap layer at least on the bottoms of the first openings; performing a thermal annealing process on the amorphous silicon layer, the cap layer and the high-K dielectric; removing the amorphous silicon layer; and forming a metal layer, in the first openings and the second openings.