Patent classifications
H01L21/76865
Semiconductor device, semiconductor memory device, and semiconductor device manufacturing method
A semiconductor device according to an embodiment includes: a semiconductor substrate; a conductor including tungsten (W) or molybdenum (Mo); a first film provided between the conductor and the semiconductor substrate and including titanium (Ti) and silicon (Si); an insulating layer surrounding the conductor; and a second film provided between the conductor and the insulating layer, surrounding the conductor, and including titanium (Ti) and nitrogen (N). A first distance between the semiconductor substrate and an end portion of the second film on a side opposite to the semiconductor substrate is smaller than a second distance between the semiconductor substrate and an end portion of the conductor on a side opposite to the semiconductor substrate.
MOLYBDENUM FILL
Embodiments of methods of filling features with molybdenum (Mo) include depositing a first layer of Mo in a feature including an opening and an interior and non-conformally treating the first layer such that regions near the opening preferentially treated over regions in the interior. In some embodiments, a second Mo layer is deposited on the treated first layer. Embodiments of methods of filling features with Mo include controlling Mo precursor flux to transition between conformal and non-conformal fill.
Conductive Interconnects and Methods of Forming Conductive Interconnects
Some embodiments include a method of forming an integrated assembly. An arrangement is formed to include a conductive pillar extending through an insulative mass. An upper surface of the conductive pillar is recessed to form a cavity. An insulative collar is formed within the cavity to line an outer lateral periphery of the cavity. A recessed surface of the conductive pillar is exposed at a bottom of the lined cavity. A conductive expanse is formed over the insulative mass. A portion of the conductive expanse extends into the cavity and is configured as an interconnect. The conductive expanse is patterned into multiple conductive structures. One of the conductive structures includes the interconnect.
SEMICONDUCTOR DEVICE
There is provided a semiconductor device capable of improving the performance and reliability of a device. The semiconductor device includes comprising a gate structure including a gate electrode and a gate capping pattern on an upper surface of the gate electrode; a source/drain pattern on at least one side of the gate structure; and a source/drain contact on and connected with an upper surface of the source/drain pattern, the source/drain contact extending along a sidewall of the gate electrode, wherein an upper surface of the source/drain contact includes a convex curved surface.
SEMICONDUCTOR STRUCTURE AND METHOD FOR PREPARING SAME
Provided are a semiconductor structure and method for preparing same. The semiconductor structure includes a gate, a source or a drain being provided in the substrate at either side of the gate; a dielectric layer; a contact structure; a first electrical connection part and a second electrical connection part arranged at intervals. The second electrical connection part is in contact with a partial top surface of the contact structure. The first electrical connection part includes a first barrier layer and a first conductive layer which are stacked. In a direction from the source to the drain, a distance between the sidewall of the first barrier layer facing the contact structure and the contact structure is a first distance, and a distance between the sidewall of the first conductive layer facing the contact structure and the contact structure is a second distance, the first distance being greater than the second distance.
Diffusion Barrier for Semiconductor Device and Method
A method includes forming an insulating layer over a conductive feature; etching the insulating layer to expose a first surface of the conductive feature; covering the first surface of the conductive feature with a sacrificial material, wherein the sidewalls of the insulating layer are free of the sacrificial material; covering the sidewalls of the insulating layer with a barrier material, wherein the first surface of the conductive feature is free of the barrier material, wherein the barrier material includes tantalum nitride (TaN) doped with a transition metal; removing the sacrificial material; and covering the barrier material and the first surface of the conductive feature with a conductive material.
BARRIER STRUCTURE FOR SEMICONDUCTOR DEVICE
Methods for making semiconductor device having improve contact structures including the operations of depositing a first dielectric material, depositing a barrier material over the first dielectric material, depositing a second dielectric material over the barrier material, etching a two-slope contact opening with an upper sidewall angle of the opening through the second dielectric material that is less than a lower sidewall angle of the opening through the first dielectric material, and filling the two-slope contact opening with a conductive material, the conductive material.
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING A THERMALLY DECOMPOSABLE LAYER, A SEMICONDUCTOR MANUFACTURING APPARATUS, AND THE SEMICONDUCTOR DEVICE
Provided are a method of manufacturing a semiconductor device using a thermally decomposable layer, a semiconductor manufacturing apparatus, and the semiconductor device. The method includes forming an etch target layer on a substrate, forming thermally decomposable patterns spaced apart from each other on the etch target layer, forming a first mask pattern covering at least sidewalls of the thermally decomposable patterns, and removing the thermally decomposable patterns by a heating method to expose a sidewall of the first mask pattern.
Integrated circuit features with obtuse angles and method of forming same
A method includes forming a seed layer on a semiconductor wafer, coating a photo resist on the seed layer, performing a photo lithography process to expose the photo resist, and developing the photo resist to form an opening in the photo resist. The seed layer is exposed, and the opening includes a first opening of a metal pad and a second opening of a metal line connected to the first opening. At a joining point of the first opening and the second opening, a third opening of a metal patch is formed, so that all angles of the opening and adjacent to the first opening are greater than 90 degrees. The method further includes plating the metal pad, the metal line, and the metal patch in the opening in the photo resist, removing the photo resist, and etching the seed layer to leave the metal pad, the metal line and the metal patch.
TREATMENT OF SPIN ON ORGANIC MATERIAL TO IMPROVE WET RESISTANCE
The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, portions of an adhesion layer, barrier layer and/or seed layer is protected by a layer of an organic mask material as portions of the adhesion layer, barrier layer and/or seed layer are removed. The layer of organic mask material is modified to improve its resistance to penetration by wet etchants used to remove exposed portions of the adhesion layer, barrier layer and/or seed layer. An example modification includes treating the layer of organic mask material with a surfactant that is absorbed into the layer of organic mask material.