A method includes etching a dielectric layer to form a trench in the dielectric layer, depositing a metal layer extending into the trench, performing a nitridation process on the metal layer to convert a portion of the metal layer into a metal nitride layer, performing an oxidation process on the metal nitride layer to form a metal oxynitride layer, removing the metal oxynitride layer, and filling a metallic material into the trench using a bottom-up deposition process to form a contact plug.

The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.

An interconnection structure includes a conductive feature disposed in a first dielectric material, a first etch stop layer disposed over the first dielectric material, a second dielectric material disposed on the first etch stop layer, a conductive via extending through the second dielectric material and the first etch stop layer and in contact with at least a portion of the conductive feature, a first barrier layer disposed between the second dielectric material and the conductive via, a first liner disposed between and in contact with the first barrier layer and the conductive via, a third dielectric material disposed over the second dielectric material, a conductive line disposed in the third dielectric material and in direct contact with the conductive via, a second barrier layer disposed on the second dielectric material and in contact with the first barrier layer and the conductive line, and a second liner disposed between and in contact with the second barrier layer and the conductive line, wherein the second liner is separated from the first liner.

Integrated circuit devices may include a fin-type active region extending on a substrate in a first horizontal direction, a gate line extending on the fin-type active region in a second horizontal direction, a source/drain region on the fin-type active region and adjacent to the gate line, and a source/drain contact pattern connected to the source/drain region. The source/drain contact pattern may include a first portion and a second portion, the first portion having a first height, and the second portion having a second height less than the first height. The source/drain contact pattern may include a metal plug in the first and second portions and a conductive barrier film on sidewalls of the metal plug in the first and second portions. A first top surface of the conductive barrier film in the second portion is lower than a top surface of the metal plug in the second portion.

A method for manufacturing a semiconductor device includes forming a first vertical transistor structure in a first device region on a substrate, and forming a second vertical transistor structure in a second device region on the substrate. The first vertical transistor structure includes a first plurality of fins, and the second vertical transistor structure includes a second plurality of fins. A plurality of first source/drain regions are grown from upper portions of the first plurality of fins, and a contact liner layer is formed on the first source/drain regions. The method further includes forming a plurality of first silicide portions from the contact liner layer on the first source/drain regions, and forming a plurality of second silicide portions on a plurality of second source/drain regions extending from upper portions of the second plurality of fins. The second silicide portions have a different composition than the first silicide portions.

There is provided a method for performing a pre-treatment to form a copper wiring in a recess formed in a substrate, which includes forming a barrier layer on a surface of the substrate that defines the recess, and forming a seed layer on the barrier layer. The method further includes at least one of etching the barrier layer and etching the seed layer. In the at least one of etching the barrier layer and etching the seed layer, the substrate is inclined with respect to an irradiation direction of ions while rotating the substrate.

Methods of fabricating semiconductor devices are provided. The method includes forming an interconnect structure over a substrate. The method also includes forming a passivation layer over the interconnect structure. The method further includes forming an opening in the passivation layer to expose a portion of the interconnect structure. In addition, the method includes sequentially forming a lower barrier film, an upper barrier film, and an aluminum-containing layer in the opening. The lower barrier film and the upper barrier film are made of metal nitride, and the upper barrier film has a nitrogen atomic percentage that is higher than a nitrogen atomic percentage of the lower barrier film and has an amorphous structure.

Package substrates including conductive interconnects having noncircular cross-sections, and integrated circuit packages incorporating such package substrates, are described. In an example, a conductive pillar having a noncircular pillar cross-section is electrically connected to an escape line routing layer. The escape line routing layer may include several series of conductive pads having noncircular pad cross-sections. Accordingly, conductive traces, e.g., strip line escapes and microstrip escapes, may be routed between the series of conductive pads in a single escape line routing layer.

A first metal interconnection pattern is formed over a substrate. A spacer layer is selectively deposited on the exposed surfaces of the first metal interconnection pattern. Subsequently, a metal overburden layer is deposited on the spacer layer. The excess portion of the metal overburden layer is removed, i.e., that portion deposited over a top surface of the metal interconnection pattern and the spacer layer. This forms a second metal interconnection pattern. The elements of the second metal interconnection pattern are located between respective elements of the first metal interconnection pattern.

A semiconductor device is provided. The semiconductor device includes: a first interlayer insulating film defining a lower wiring trench; a lower wiring structure including a first lower barrier film which extends along sidewalls of the lower wiring trench, and a lower filling film which is on the first lower barrier film; a second interlayer insulating film on the first interlayer insulating film, the second interlayer insulating film defining an upper wiring trench which exposes at least part of the lower wiring structure; and an upper wiring structure provided in the upper wiring trench and connected to the lower wiring structure. An upper surface of the first lower barrier film is closer to a bottom surface of the lower wiring trench than each of an upper surface of the first interlayer insulating film and an upper surface the lower filling film. The upper surface of the first lower barrier film is concave.