Methods and apparatus for forming a barrier layer are provided herein. In some embodiments, a method of forming a barrier layer on a substrate includes treating an exposed layer deposited on a substrate and within a feature of the substrate by pulsing a bias power applied to a substrate support supporting the substrate while exposing the layer to a plasma. The exposed layer can be deposited by an atomic layer deposition process, and can be, for example, a tantalum nitride layer. The bias power can be up to 500 watts of RF power at a pulse frequency of about 1 Hz to about 10 kHz. The bias power can be pulsed uniformly or at multiple different levels.

A method for forming a gate structure includes forming a trench within an interlayer dielectric layer (ILD) that is disposed on a semiconductor substrate, the trench exposing a top surface of the semiconductor substrate, forming an interfacial layer at a bottom of the trench, forming a dielectric layer within the trench, forming a work function metal layer on the dielectric layer, forming an in-situ nitride layer on the work function metal layer in the trench, performing a first cobalt deposition process to form a cobalt layer within the trench, performing a second cobalt deposition process to increase a thickness of the cobalt layer within the trench, and performing an electrochemical plating (ECP) process to fill the trench with cobalt.

A semiconductor may include a first inter metal dielectric (IMD) layer, a first blocking layer on the first IMD layer, a metal wiring and a second blocking layer. The first inter metal dielectric (IMD) layer may be formed on a substrate, the first IMD layer may include a low-k material having a dielectric constant lower than a dielectric constant of silicon oxide. The first blocking layer may be formed on the first IMD layer. The first blocking layer may include an oxide having a dielectric constant higher than the dielectric constant of the first IMD layer. The metal wiring may be through the first IMD layer and the first blocking layer. The second blocking layer may be formed on the metal wiring and the first blocking layer. The second blocking layer may include a nitride. The first and second blocking layers may reduce or prevent from the out gassing, so that a semiconductor device may have good characteristics.

This application discloses a coating method for making a chip. The method includes: fixing a substrate on a base. The substrate includes a hole. The method includes controlling an included angle between a plane on which the substrate is located and a deposition direction of a coating material to be greater than 0 degrees and less than 90 degrees. The method includes controlling the substrate to rotate with respect to an axis perpendicular to the plane on which the substrate is located. The method includes during the rotation of the substrate, controlling the coating material to enter the hole along the deposition direction such that the coating material is deposited on a sidewall of the hole.

A semiconductor device includes a first dielectric layer over a device base layer, the first dielectric layer having a first opening with a first sidewall; a first interconnect segment extending through the first opening; and a cap layer over a top surface of the first interconnect segment, wherein the cap layer comprises a first metal, carbon, and nitrogen.

A method of depositing a metal material on an isolated seed layer uses a barrier layer as a conductive path for plating. The method may include depositing a barrier layer on a substrate wherein the barrier layer provides adhesion for seed layer material and inhibits migration of the seed layer material, forming at least one isolated seed layer area on the barrier layer on the substrate, and depositing the metal material on the at least one isolated seed layer area using an electrochemical deposition process wherein the barrier layer provides a current path to deposit the metal material on the at least one isolated seed layer area.

Some of the embodiments of the present application provide a semiconductor structure and a method of manufacturing the same, the method of manufacturing the semiconductor structure comprising: providing a base; performing a first electroplating process to form a first electroplated layer on the base; performing a second electroplating process to form a second electroplated layer on the surface of the first electroplated layer, the current density of the second electroplated layer being greater than the current density of the first electroplated layer.

A method of forming a metal-insulator-metal (MIM) capacitor with copper top and bottom plates may begin with a copper interconnect layer (e.g., Cu MTOP) including a copper structure defining the capacitor bottom plate. A passivation region is formed over the bottom plate, and a wide top plate opening is etched in the passivation region, to expose the bottom plate. A dielectric layer is deposited into the top plate opening and onto the exposed bottom plate. Narrow via opening(s) are then etched in the passivation region. The wide top plate opening and narrow via opening(s) are concurrently filled with copper to define a copper top plate and copper via(s) in contact with the bottom plate. A first aluminum bond pad is formed on the copper top plate, and a second aluminum bond pad is formed in contact with the copper via(s) to provide a conductive coupling to the bottom plate.

A method for performing an electrochemical plating (ECP) process includes contacting a surface of a substrate with a plating solution comprising ions of a metal to be deposited, electroplating the metal on the surface of the substrate, in situ monitoring a plating current flowing through the plating solution between an anode and the substrate immersed in the plating solution as the ECP process continues, and adjusting a composition of the plating solution in response to the plating current being below a critical plating current such that voids formed in a subset of conductive lines having a highest line-end density among a plurality of conductive lines for a metallization layer over the substrate are prevented.

A process for forming cobalt on a substrate, comprising: volatilizing a cobalt precursor of the disclosure, to form, a precursor vapor: and contacting the precursor vapor with the substrate under vapor deposition conditions effective for depositing cobalt on the substrate from the precursor vapor, wherein the vapor deposition conditions include temperature not exceeding 200° C., wherein: the substrate includes copper surface and dielectric material, e.g., ultra-low dielectric material. Such cobalt deposition process can be used to manufacture product articles in which the deposited cobalt forms a capping layer, encapsulating layer, electrode, diffusion layer, or seed for electroplating of metal thereon, e.g., a semiconductor device, flat-panel, display, or solar panel. A cleaning composition containing base and oxidizing agent components may be employed to clean the copper prior to deposition of cobalt thereon, to achieve substantially reduced defects in the deposited cobalt.