A method of forming a semiconductor structure includes forming a semiconductor device over a substrate, forming a combination of a connection-level dielectric layer and a connection-level metal interconnect structure over the semiconductor device, where the connection-level metal interconnect structure is electrically connected to a node of the semiconductor device and is embedded in the connection-level dielectric layer, forming a line-and-via-level dielectric layer over the connection-level dielectric layer, forming an integrated line-and-via cavity through the line-and-via-level dielectric layer over the connection-level metal interconnect structure, selectively growing a conductive via structure containing cobalt from a bottom of the via portion of the integrated line-and-via cavity without completely filling a line portion of the integrated line-and-via cavity, and forming a copper-based conductive line structure that contains copper at an atomic percentage that is greater than 90% in the line portion of the integrated line-and-via cavity on the conductive via structure.

A semiconductor device is provided. The semiconductor device includes a first insulating interlayer disposed on a first surface of a substrate; a pad pattern disposed on a lower surface of the first insulating interlayer, the pad pattern including a first copper pattern; and a through silicon via passing through the substrate and the first insulating interlayer, and contacting the first copper pattern of the pad pattern. The through silicon via includes a first portion passing through the substrate and the first insulating interlayer, and a second portion under the first portion and extending to a portion of the first copper pattern in the pad pattern. A boundary of the through silicon via has a bent portion between the first portion and the second portion.

An electrochemical plating (ECP) system is provided. The ECP system includes an ECP cell comprising a plating solution for an ECP process, a sensor configured to in situ measure an interface resistance between a plated metal and an electrolyte in the plating solution as the ECP process continues, a plating solution supply system in fluid communication with the ECP cell and configured to supply the plating solution to the ECP cell, and a control system operably coupled to the ECP cell, the sensor and the plating solution supply system. The control system is configured to compare the interface resistance with a threshold resistance and to adjust a composition of the plating solution in response to the interface resistance being below the threshold resistance.

Exemplary methods of electroplating include contacting a patterned substrate with a plating bath in an electroplating chamber, where the pattern substrate includes at least one opening having a bottom surface and one or more sidewall surfaces. The methods may further include forming a nanotwin-containing metal material in the at least one opening. The metal material may be formed by two or more cycles that include delivering a forward current from a power supply through the plating bath of the electroplating chamber for a first period of time, plating a first amount of the metal on the bottom surface of the opening on the patterned substrate and a second amount of the metal on the sidewall surfaces of the opening, and delivering a reverse current from the power supply through the plating bath of the electroplating chamber to remove some of the metal plated in the opening on the patterned substrate.

Exemplary methods of electroplating may include providing a patterned substrate having at least one opening, where the opening includes one or more sidewalls and a bottom surface. The methods may also include plating a first portion of ruthenium-containing material on the bottom surface of the opening at a first deposition rate and a second portion of ruthenium-containing material on the sidewalls of the opening at a second deposition rate, where the first deposition rate is greater than the second deposition rate. The methods may be used to make integrated circuit devices that include void-free, electrically-conductive lines and columns of ruthenium-containing materials.

A semiconductor package includes; a first redistribution structure including first redistribution conductors, a semiconductor chip on the first redistribution structure and including connection pads electrically connecting the first redistribution conductors, a connection conductor on the first redistribution structure, laterally spaced apart from the semiconductor chip, and electrically connected to the first redistribution conductors, an encapsulant on the first redistribution structure and sealing the semiconductor chip and at least a portion of the connection conductor, a barrier layer extending along an upper surface of the encapsulant, and a second redistribution conductor on the barrier layer and penetrating the barrier layer to contact the connection conductor.

Exemplary methods of electroplating include contacting a patterned substrate with a plating bath in an electroplating chamber, where the pattern substrate includes at least one opening having a bottom surface and one or more sidewall surfaces. The methods may further include forming a nanotwin-containing metal material in the at least one opening. The metal material may be formed by two or more cycles that include delivering a forward current from a power supply through the plating bath of the electroplating chamber for a first period of time, plating a first amount of the metal on the bottom surface of the opening on the patterned substrate and a second amount of the metal on the sidewall surfaces of the opening, and delivering a reverse current from the power supply through the plating bath of the electroplating chamber to remove some of the metal plated in the opening on the patterned substrate.

Exemplary methods of electroplating may include providing a patterned substrate having at least one opening, where the opening includes one or more sidewalls and a bottom surface. The methods may also include plating a first portion of ruthenium-containing material on the bottom surface of the opening at a first deposition rate and a second portion of ruthenium-containing material on the sidewalls of the opening at a second deposition rate, where the first deposition rate is greater than the second deposition rate. The methods may be used to make integrated circuit devices that include void-free, electrically-conductive lines and columns of ruthenium-containing materials.

In an embodiment, a device includes: a molding compound; an integrated circuit die encapsulated in the molding compound; a through via adjacent the integrated circuit die; and a redistribution structure over the integrated circuit die, the molding compound, and the through via, the redistribution structure electrically connected to the integrated circuit die and the through via, the redistribution structure including: a first dielectric layer disposed over the molding compound; a first conductive via extending through the first dielectric layer; a second dielectric layer disposed over the first dielectric layer and the first conductive via; and a second conductive via extending through the second dielectric layer and into a portion of the first conductive via, an interface between the first conductive via and the second conductive via being non-planar.

A method of forming a semiconductor structure and a semiconductor structure are provided. The method of forming the semiconductor structure includes: providing a base, where the base includes a first dielectric layer and pads arranged at intervals in the first dielectric layer; forming a dielectric structure, where the dielectric structure exposes the pad and part of the first dielectric layer; forming an insulating structure, where the insulating structure is formed on a sidewall of the dielectric structure, the insulating structure covers a first partial sidewall of the dielectric structure, and an air gap is formed between a second partial sidewall of the dielectric structure and the insulating structure; and forming a conductive structure, where the conductive structure covers an exposed pad and an outer sidewall surface of the insulating structure.