An integrated circuit structure includes a first interconnect layer including a first dielectric material. The first dielectric material has a first recess therein, the first recess having a first opening. The integrated circuit structure further includes a second interconnect layer above the first interconnect layer. The second interconnect layer includes a second dielectric material that has a second recess therein. The second recess has a second opening. In an example, at least a portion of the first opening of the first recess abuts and overlaps with at least a portion of the second opening of the second recess. In an example, a continuous conformal layer is on walls of the first and second recesses, and a continuous body of conductive material is within the first and second recesses.

A via for semiconductor devices is disclosed. Implementations of vias for semiconductor devices may include: a semiconductor substrate that includes a first side; a via extending from the first side of the semiconductor substrate to a pad; a polymer layer coupled along an entire sidewall of the via, the polymer layer in direct contact with the pad; and a metal layer directly coupled over the polymer layer and directly coupled with the pad.

An apparatus for electroplating includes a cup configured to support a substrate, and a cone including at least three distance measuring devices arranged on a lower surface thereof and facing the substrate. Each distance measuring device is configured to transmit a laser pulse towards the substrate, the laser pulse impinging the substrate, receive a reflected laser pulse from the substrate, calculate a turnaround time of the laser pulse, and calculate a distance between the distance measuring device and the substrate using the turnaround time for determining an inclination of the substrate.

A Cu interconnect having a diffusion barrier formed with the self-formed high-entropy alloy a method of preparing the same are provided. A high-entropy alloy and Cu are deposited together. When annealing, a diffusion barrier is formed through segregation of the high-entropy alloy may, toward a bottom and a sidewall of an interconnect via, and a Cu seed layer is formed through segregation of Cu at an outer surface of the diffusion barrier, so as to simultaneously self-form the diffusion barrier formed with the self-formed high-entropy alloy and the Cu seed layer. The Cu interconnect having a diffusion barrier formed with the self-formed high-entropy alloy comprises: a base, the self-formed diffusion barrier formed with the self-formed high-entropy alloy and the Cu seed layer and a Cu electroplating layer electroplating on the Cu seed layer.

Methods/structures of forming substrate tap structures are described. Those methods/structures may include forming a plurality of conductive interconnect structures on an epitaxial layer disposed on a substrate, wherein individual ones of the plurality of conductive interconnect structures are adjacent each other, forming a portion of a seed layer on at least one of the plurality of conductive interconnect structures, and forming a conductive trace on the seed layer.

A process of forming a semiconductor device that includes an interconnection formed by electro-plating is disclosed. The process comprises steps of: forming a stopper layer on the first insulating film; covering the stopper layer and the first insulating film with a second insulating film; preparing a first mask having an edge that overlaps with the stopper layer; depositing a seed layer on the first mask and the second insulating film that is exposed from the first mask; preparing a second mask having an edge that overlaps with the stopper layer, the edge of the first mask retreating from the edge of the second mask; forming an upper layer on the seed layer by electro-plating a metal so as not to overlap with the first mask; and removing the seed layer exposed from the upper layer by etching.

There is provided a method for performing a pre-treatment to form a copper wiring in a recess formed in a substrate, which includes forming a barrier layer on a surface of the substrate that defines the recess, and forming a seed layer on the barrier layer. The method further includes at least one of etching the barrier layer and etching the seed layer. In the at least one of etching the barrier layer and etching the seed layer, the substrate is inclined with respect to an irradiation direction of ions while rotating the substrate.

Described herein is a composition for depositing copper on a semiconductor substrate, the composition including

(a) copper ions;
(b) an additive of formula S1

##STR00001##

(c) a complexing agent; and
(d) optionally a buffer or base capable of adjusting the pH to a pH of from 7 to 13;
where the variables are as defined herein; and
where the pH of the composition is from 7 to 13 and where the composition is free of any cyanide.

Various embodiments relate to methods, apparatus, and systems for forming an interconnect structure, or a portion thereof. The method may include contacting the substrate with a functionalization bath comprising a first solvent and a functionalization reactant to form a modified first material, and then depositing a second material on the modified first material through electroless plating, electroplating, chemical vapor deposition, or atomic layer deposition. The first material may be a dielectric material, a barrier layer, or a liner, and the second material may be a barrier layer or a barrier layer precursor, a liner, a seed layer, or a conductive metal that forms the interconnect of the interconnect structure, according to various embodiments.

A method includes depositing a metallic hardmask over a dielectric layer. The method further includes etching a metallic hardmask opening in the metallic hardmask to expose a top surface of the dielectric layer. The method further includes modifying a sidewall of the metallic hardmask opening by adding non-metal atoms into the metallic hardmask. The method further includes depositing a conductive material in the metallic hardmask opening.