The disclosure discloses a copper plating filling process method, comprising the steps of: forming a trench or a through-hole in a dielectric layer; forming a copper seed layer on an inner surface of the hole; allowing a waiting time after forming the copper seed layer and before performing a copper plating process, wherein during the waiting time, a surface of the copper seed layer is oxidized to form a copper oxide layer; performing a reduction process on the copper oxide layer; and filling a copper layer into the hole in the copper plating process afterwards. The copper oxide layer on the surface of the copper seed layer is reduced to copper in the reduction process, and wherein a thickness of the copper seed layers on the inner surface of the hole is uniform. The hole can be a trench or a through-hole.

A semiconductor device includes a semiconductor part; an electrode selectively provided on the semiconductor part, the electrode being electrically connected to the semiconductor part; and multiple metal layers provided on the electrode. A method of manufacturing the semiconductor device includes selectively forming a first metal layer on the electrode; forming a palladium layer on the first metal layer, the palladium layer covering the first metal layer; forming a second metal layer on the palladium layer, the second metal layer covering the palladium layer; and forming a gold layer directly on the palladium layer by replacing the second metal layer with the gold layer.

A multilayer wiring forming method includes forming, in a via 70 formed at a preset position in an insulating film 60 provided on a wiring 50 of a substrate, the via 70 being extended to the wiring 70, a monomolecular film 80 on a bottom surface 73 at which the wiring 50 is exposed; forming a barrier film 81 on a side surface 72 of the via 70; removing the monomolecular film 80; and forming an electroless plating film 82 from the bottom surface 73 of the via 70 by using the wiring 50 exposed at the bottom surface 73 of the via 70 as the catalyst.

Disclosed embodiments include a catalyst-doped mold interconnect system, where activated catalyst particles that line via and trace corridors, are used for electroless-plating formation of both liners and vias and traces that also electrolessly plate onto the liners. Photolithographically formed interconnects can be mingled with laser-ablation form-factor vias and traces within a single stratum of a catalyst doped mold interconnect system.

A method for manufacturing a wiring substrate includes forming multiple conductor pads on an insulating layer such that the conductor pads include multiple first conductor pads and multiple second conductor pads, forming multiple protruding parts on surfaces of the first conductor pads of the conductor pads, respectively, forming a resin layer such that the resin layer covers the insulating layer and the conductor pads, exposing, from the resin layer, end portions of the protruding parts on the opposite side with respect to the insulating layer, forming, in the resin layer, multiple openings such that the openings expose surfaces of the second conductor pads of the conductor pads, respectively; and forming a coating film on the surfaces of the second conductor pads exposed in the openings.

A method includes a step of performing a selective catalyst treatment by supplying a catalyst solution to an upper surface of an exposed interconnection layer forming a step portion of a stepped shape formed by pair layers stacked to form the stepped shape, the pair layer including an interconnection layer formed on an insulating layer, and a step of selectively growing a metal layer by performing electroless plating on the upper surface of the interconnection layer on which the catalyst treatment is performed.

An embodiment is a method including forming an opening in a mask layer, the opening exposing a conductive feature below the mask layer, forming a conductive material in the opening using an electroless deposition process, the conductive material forming a conductive via, removing the mask layer, forming a conformal barrier layer on a top surface and sidewalls of the conductive via, forming a dielectric layer over the conformal barrier layer and the conductive via, removing the conformal barrier layer from the top surface of the conductive via, and forming a conductive line over and electrically coupled to the conductive via.

A method for manufacturing a conductive laminate and a conductive laminate are provided. The method for manufacturing the conductive laminate includes steps of: providing a substrate having a surface; immersing the substrate into a modifying solution including a silane with a hydrophilic group to form a discontinuous modified layer on the surface of the substrate; forming a barrier layer on the surface of the substrate and the discontinuous modified layer, and forming a conductive layer on a surface of the barrier layer. The barrier layer includes a polymer, and the polymer is selected from the group consisting of: polyvinyl alcohol, polyvinylpyrrolidone, polyacrylic acid, polyethylene glycol, and any combination thereof.

There is provided a technique capable of forming a plating film excellent in film thickness and quality uniformity on a to-be-plated surface of a semiconductor wafer while suppressing an increase in costs of facilities. An apparatus for manufacturing a semiconductor device includes: a reaction bath; a supply pipe provided inside the reaction bath and including a plurality of ejection holes for ejecting the reaction solution, the ejecting holes being arranged in a longitudinal direction of the supply pipe; and an outer bath serving as a reservoir bath provided adjacent to the reaction bath on a first end side of the supply pipe and storing therein the reaction solution overflowed the reaction bath. The aperture ratio of part of the ejection holes more distant from the outer bath is at least partially higher than that of part of the ejection holes closer to the outer bath.

Provided is a method of forming an interconnect structure including: forming a via; forming a first barrier layer to at least cover a top surface and a sidewall of the via; forming a first dielectric layer on the first barrier layer; performing a planarization process to remove a portion of the first dielectric layer and a portion of the first barrier layer, thereby exposing the top surface of the via; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer has an opening exposing the top surface of the via; forming a blocking layer on the top surface of the via; forming a second barrier layer on the second dielectric layer; removing the blocking layer to expose the top surface of the via; and forming a conductive feature in the opening, wherein the conductive feature is in contact with the top surface of the via.