A method for manufacturing a semiconductor device includes forming a plurality of trenches in a dielectric layer, wherein the plurality of trenches each comprise a rounded surface, depositing a liner layer on the rounded surface of each of plurality of trenches, and depositing a conductive layer on the liner layer in each of the plurality of trenches, wherein the conductive layer and the liner layer form a plurality of interconnects, and each of the plurality of interconnects has a cylindrical shape.

A semiconductor package structure includes a conductive trace layer, a semiconductor die over the conductive trace layer, a structure enhancement layer surrounding the semiconductor die, and an encapsulant covering the semiconductor die and the structure enhancement layer. The structure enhancement layer coincides with a mass center plane of the semiconductor package structure. The mass center plane is parallel to a top surface of the semiconductor die. A method for manufacturing the semiconductor package structure is also provided.

Disclosed embodiments include a catalyst-doped mold interconnect system, where activated catalyst particles that line via and trace corridors, are used for electroless-plating formation of both liners and vias and traces that also electrolessly plate onto the liners. Photolithographically formed interconnects can be mingled with laser-ablation form-factor vias and traces within a single stratum of a catalyst doped mold interconnect system.

A substrate processing method is provided for performing a plating processing on a substrate having, on a surface thereof, an impurity-doped polysilicon film containing a high concentration of impurities. The substrate processing method includes forming a catalyst layer by supplying, onto the substrate, an alkaline catalyst solution containing a complex of a palladium ion and a monocyclic 5- or 6-membered heterocyclic compound having one or two nitrogen atoms as a heteroatom; and forming a plating layer through electroless plating by supplying a plating liquid onto the substrate after the forming of the catalyst layer.

The present disclosure relates to a shielded electronic module, which includes a module substrate, an electronic component attached to a top surface of the module substrate and encapsulated by a first mold compound, a second mold compound over a bottom surface of the module substrate, and a shielding structure. The second mold compound includes a recess extending inwardly from a bottom periphery of the second mold compound. The shielding structure completely covers a top surface of the module and extends over the side surface of the module until reaching the recess. Herein, the shielding structure is electrically grounded.

A semiconductor device includes a semiconductor part; an electrode selectively provided on the semiconductor part, the electrode being electrically connected to the semiconductor part; and multiple metal layers provided on the electrode. A method of manufacturing the semiconductor device includes selectively forming a first metal layer on the electrode; forming a palladium layer on the first metal layer, the palladium layer covering the first metal layer; forming a second metal layer on the palladium layer, the second metal layer covering the palladium layer; and forming a gold layer directly on the palladium layer by replacing the second metal layer with the gold layer.

A multilayer wiring forming method includes filling a via, which is formed in an insulating film including an oxide film formed on a wiring of a substrate and is extended to the wiring, by forming an electroless plating film, which does not diffuse into the oxide film, from a bottom surface of the via while using the wiring, which is exposed at the bottom surface of the via, as a catalyst.

A semiconductor structure includes an etching stop layer over an inter-layer dielectric (ILD) layer; a low-k dielectric layer over the etching stop layer; and a tapered conductor extending through the low-k dielectric layer and the etching stop layer and partially through the ILD layer; wherein the tapered conductor includes a recess disposed within the ILD layer and indented towards the etching stop layer and the low-k dielectric layer, and a protrusion surrounding the recess and protruded from the etching stop layer towards the ILD layer.

A semiconductor integrated circuit comprises a semiconductor substrate having a via-hole, a front-side-metal layer formed on a top surface of the semiconductor substrate, a seed-metal layer and a backside-metal layer. A bottom surface of an inner surface of the via-hole is at least partially defined by the front-side-metal layer. A surrounding surface of the inner surface of the via-hole is at least partially defined by the semiconductor substrate. The seed-metal layer is formed on the inner surface of the via-hole and a bottom surface of the semiconductor substrate such that the seed-metal layer and the front-side-metal layer are connected. The backside-metal layer is formed on an outer surface of the seed-metal layer. An aspect ratio of the via-hole is greater than or equal to 0.2 and less than or equal to 3, thereby a thickness uniformity of the backside-metal layer is improved.

A filter structure comprises a first dielectric buildup film. A second dielectric buildup film is over the first dielectric buildup film, the second dielectric buildup film including a metallization catalyst. A trench is in the second dielectric buildup film. A metal is selectively plated to sidewalls of the trench based at least in part on the metallization catalyst. A low-loss buildup film is over the metal that substantially fills the trench.