A device package and a method of forming a device package are described. The device package includes an interposer with interconnects on an interconnect package layer and a conductive layer on the interposer. The device package has dies on the conductive layer, where the package layer includes a zero-misalignment two-via stack (ZM2VS) and a dielectric. The ZM2VS is directly coupled to the interconnect. The ZM2VS may further include the dielectric on a conductive pad, a first via on a first seed, and the first seed on a top surface of the conductive pad, where the first via extends through dielectric. The ZM2VS may also have a conductive trace on dielectric, and a second via on a second seed, the second seed is on the dielectric, where the conductive trace connects to first and second vias, where second via connects to an edge of conductive trace opposite from first via.

A method and apparatus for processing a substrate are described herein. The methods and apparatus described enable the raising and lowering of a shadow ring within a process chamber either simultaneously with or separately from a plurality of substrate lift pins. The shadow ring is raised and lowered using a shadow ring lift assembly and may be raised to a pre-determined height above the substrate during a radical treatment operation. The shadow ring lift assembly may also raise and lower the plurality of substrate lift pins to enable both the shadow ring and the substrate lift pins to be raised to a transfer position when the substrate is being transferred into or out of the process chamber.

A three-dimensional memory device includes a vertical repetition of multiple instances of a unit layer stack, memory openings vertically extending through the vertical repetition, and memory opening fill structures located within the memory openings. Each of the memory opening fill structures contains a respective vertical stack of memory elements. The unit layer stack includes, from bottom to top or from top to bottom, a cavity-free insulating layer that is free of any cavity therein, a first-type electrically conductive layer, a cavity-containing insulating layer including an encapsulated cavity therein, and a second-type electrically conductive layer.

A method may include providing a device structure in the semiconductor device. The device structure may include a buried device contact, a first dielectric layer, disposed over the buried device contact; and a device element, where the device element includes a TiN layer. The method may include implanting an ion species into the TiN layer, wherein the ion species comprises a seed material for selective tungsten deposition.

A film deposition method includes preparing a substrate having an insulating film formed thereon, forming a seed layer on the insulating film, and supplying a molybdenum-containing gas and a reducing gas to the substrate having the seed layer famed thereon, to foam a molybdenum film on the seed layer.

Embodiments of methods of filling features with molybdenum (Mo) include depositing a first layer of Mo in a feature including an opening and an interior and non-conformally treating the first layer such that regions near the opening preferentially treated over regions in the interior. In some embodiments, a second Mo layer is deposited on the treated first layer. Embodiments of methods of filling features with Mo include controlling Mo precursor flux to transition between conformal and non-conformal fill.

Methods of forming a tungsten film comprising forming a boron seed layer on an oxide surface, an optional tungsten initiation layer on the boron seed layer and a tungsten containing film on the boron seed layer or tungsten initiation layer are described. Film stack comprising a boron seed layer on an oxide surface with an optional tungsten initiation layer and a tungsten containing film are also described.

A semiconductor device structure is provided. The semiconductor device structure includes a first stacked nanostructure and a second stacked nanostructure formed over a substrate, and a dummy fin structure between the first stacked nanostructure and the second stacked nanostructure. The semiconductor device structure includes a gate structure formed over the first stacked nanostructure and the second stacked nanostructure, and a conductive layer formed over the gate structure. The semiconductor device structure includes a capping layer formed over the dummy fin structure, and each of the gate structure and the conductive layer is divided into two portions by the capping layer.

Described herein are methods of filling features with tungsten and related apparatus. The methods described herein involve deposition of a tungsten nucleation layer prior to deposition of a bulk layer. The methods involve multiple atomic layer deposition (ALD) cycles. According to various embodiments, both a boron-containing reducing agent and silicon-reducing agent may be pulses during a single cycle to react with a tungsten-containing precursor and form a tungsten film.

The disclosed technology generally relates to forming a titanium nitride layer, and more particularly to forming by atomic layer deposition a titanium nitride layer on a seed layer. In one aspect, a semiconductor structure comprises a semiconductor substrate comprising a non-metallic surface. The semiconductor structure additionally comprises a seed layer comprising silicon (Si) and nitrogen (N) conformally coating the non-metallic surface and a TiN layer conformally coating the seed layer. Aspects are also directed to methods of forming the semiconductor structures.