According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a co-catalyst layer and catalyst layer above a surface of a semiconductor substrate. The co-catalyst layer and catalyst layer have fcc structure. The fcc structure is formed such that (111) face of the fcc structure is to be oriented parallel to the surface of the semiconductor substrate. The catalyst includes a portion which contacts the co-catalyst layer. The portion has the fcc structure. An exposed surface of the catalyst layer is planarized by oxidation and reduction treatments. A graphene layer is formed on the catalyst layer.

The disclosed technology relates to integrate circuits, including memory devices. A method of forming an integrated circuit comprises providing a surface comprising a first region and a second region, wherein the first region is formed of a different material than the second region. The method additionally comprises forming a seeding material in contact with and across the first and second regions. The method further comprises forming a metal comprising tungsten on the seeding material.

A method is provided for fabricating an interconnect structure. The method includes providing a substrate; and forming a first conductive layer; and forming a sacrificial layer on the substrate and the first conductive layer. The method also includes forming an opening exposing a surface of the first conductive layer in the sacrificial layer; and forming a catalyst layer on the exposed portion of the surface of the first conductive layer and a top surface of the sacrificial layer. Further, the method includes forming carbon nanotube bundles perpendicular to the surface of the substrate on the catalyst layer; and removing the sacrificial layer and the carbon bundles on the sacrificial layer. Further, the method also includes forming a first dielectric material layer covering top surfaces of the carbon nanotube bundles and a portion the surface of the substrate without carbon nanotubes to seal the carbon nanotube bundles in a space.

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive feature in the dielectric layer, and the conductive feature includes a catalyst layer and a conductive element. The catalyst layer is between the conductive element and the dielectric layer, and the catalyst layer is in physical contact with the conductive element. The catalyst layer continuously surrounds a sidewall and a bottom of the conductive element. The catalyst layer is made of a material different from that of the conductive element, and the catalyst layer is capable of lowering a formation temperature of the conductive element.

A method for manufacturing a semiconductor device includes providing a substrate, performing a nucleation process on the substrate to form a nucleation layer of a metal, performing a first deposition process at a first temperature on the nucleation layer to form a first layer of the metal, etching back the first layer of the metal using a first gas, cleaning the substrate including the etched back first layer of the metal using a second gas, and performing a second deposition process to form a second layer of the metal on the etched back first layer of the metal. By cleaning the substrate and the etched-back first layer of the metal using the second gas, the thickness fluctuation of the deposited metal layer from wafer to wafer is significantly reduced.

An apparatus includes a housing, a chamber disposed in the housing and configured to receive a substrate, a shower head disposed outside the housing and configured to supply a process gas to the chamber, and a hot wire at a first temperature disposed between the shower head and the substrate. The hot wire at the first temperature ionizes the process gas, and the ionized gas is supplied to the substrate for performing a hot-wire assisted plasma-assisted pre-cleaning process and a hot-wire assisted atomic layer deposition process. The apparatus also includes a hot plate in the chamber and configured to bring the substrate to a second temperature.

Examples of an integrated circuit with an interconnect structure that includes a buried interconnect conductor and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a substrate that includes a plurality of fins extending from a remainder of the substrate. A spacer layer is formed between the plurality of fins, and a buried interconnect conductor is formed on the spacer layer between the plurality of fins. A set of capping layers is formed on the buried interconnect conductor between the plurality of fins. A contact recess is etched through the set of capping layers that exposes the buried interconnect conductor, and a contact is formed in the contact recess that is electrically coupled to the buried interconnect conductor.

A device includes a non-insulator structure, a first dielectric layer, and a first conductive feature. The first dielectric layer is over the non-insulator structure. The first conductive feature is in the first dielectric layer and includes carbon nano-tubes. The first catalyst layer is between the first conductive feature and the non-insulator structure. A top of the first catalyst layer is lower than a top of the first conductive feature.

A semiconductor memory device includes a first region where a plurality of conductive layers, a plurality of insulating layers, a semiconductor layer, and a gate insulating layer are formed and a second region different from the first region above a substrate. The plurality of conductive layers include a plurality of first conductive layers and a plurality of second conductive layers. The semiconductor memory device includes a plurality of first films different from the first conductive layers disposed in same layers as the plurality of first conductive layers in the second region and a plurality of second films different from the second conductive layers and the first films disposed in same layers as the plurality of second conductive layers in the second region.

The present disclosure provides an interconnect structure, including a substrate, a first conductive feature over the substrate, a second conductive feature over the first conductive feature, and a dielectric layer surrounding the first conductive feature and the second conductive feature. A width of the first conductive feature and a width of the second conductive feature are between 10 nm and 50 nm. The present disclosure also provides a method for manufacturing an interconnect structure, including (1) forming a via opening and a line trench in a dielectric layer, (2) forming a 1-dimensional conductive feature in the via opening, (3) forming a conformal catalyst layer over a sidewall of the line trench, a bottom of the line trench, and a top of the 1-dimensional conductive feature, and (4) removing the conformal catalyst layer from the bottom of the line trench and the top of the 1-dimensional conductive feature.