A method of manufacturing a semiconductor device includes: forming an amorphous metal film on a substrate by time-divisionally conducting a cycle a predetermined number of times, the cycle including: (a) simultaneously supplying a metal-containing gas and a first reducing gas to the substrate to form a first amorphous metal layer on the substrate, and (b) forming a second amorphous metal layer on the first amorphous metal layer by time-divisionally supplying, a predetermined number of times, the metal-containing gas and a second reducing gas to the substrate on which the first amorphous metal layer is formed; and forming a crystallized metal layer on the substrate by simultaneously supplying the metal-containing gas and the first reducing gas to the substrate on which the amorphous metal film is formed.

A method is provided for producing at least one electrical via in a substrate, the method comprising: producing a protective layer over a component structure which has been produced or is present on a front side of the substrate; forming at least one contact hole which extends from a surface of a backside of the substrate to a contact surface of the component structure; forming a metal-containing and thus conductive lining in the at least one contact hole creating a hollow electrically conductive structure in the at least one contact hole; and applying a passivation layer over the backside of the substrate, the passivation layer spanning over the hollow electrically conductive structure for forming the at least one electrical via. Also provided is a micro-technical component comprising at least one electrical via.

A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes.

A semiconductor arrangement is provided. The semiconductor arrangement includes a dielectric layer defining an opening, an adhesion layer in the opening, and a conductive layer in the opening over the adhesion layer. A material of the conductive layer is a same material as an adhesion material of the adhesion layer.

A silicon film forming method of forming a silicon film in a recess with respect to a target substrate having on its surface an insulating film in which the recess is formed. The method includes (a) forming a first silicon film filling the recess by supplying a Silicon raw material gas onto the target substrate, (b) subsequently, etching the first silicon film by supplying a halogen-containing etching gas onto the target substrate such that surfaces of the insulating film on the target substrate and on an upper portion of an inner wall of the recess are exposed and such that the first silicon film remains in a bottom portion of the recess, and (c) subsequently, growing a second silicon film in a bottom-up growth manner on the first silicon film that remains in the recess by supplying a Silicon raw material gas onto the target substrate after the etching.

Aspects of the methods and apparatus described herein relate to deposition of tungsten nucleation layers and other tungsten-containing films. Various embodiments of the methods involve exposing a substrate to alternating pulses of a tungsten precursor and a reducing agent at low chamber pressure to thereby deposit a tungsten-containing layer on the surface of the substrate. According to various embodiments, chamber pressure may be maintained at or below 10 Torr. In some embodiments, chamber pressure may be maintained at or below 7 Torr, or even lower, such as at or below 5 Torr. The methods may be implemented with a fluorine-containing tungsten precursor, but result in very low or undetectable amounts of fluorine in the deposited layer.

Provided herein are methods of depositing void-free cobalt into features with high aspect ratios. Methods involve (a) partially filling a feature with cobalt, (b) exposing the feature to a plasma generated from nitrogen-containing gas to selectively inhibit cobalt nucleation on surfaces near or at the top of the feature, optionally repeating (a) and (b), and depositing bulk cobalt into the feature by chemical vapor deposition. Methods may also involve exposing a feature including a barrier layer to a plasma generated from nitrogen-containing gas to selectively inhibit cobalt nucleation. The methods may be performed at low temperatures less than about 400° C. using cobalt-containing precursors. Methods may also involve using a remote plasma source to generate the nitrogen-based plasma. Methods also involve annealing the substrate.

Methods for depositing a metal film on a doped amorphous silicon layer as a nucleation layer and/or a glue layer on a substrate. Some embodiments further comprise the incorporation of a glue layer to increase the ability of the doped amorphous silicon layer and metal layer to stick to the substrate.

Described are methods for forming a tungsten conductive structure over a substrate, such as a semiconductor substrate. Described examples include forming a silicon-containing material, such as a doped silicon-containing material, over a supporting structure. The silicon-containing material is then subsequently converted to a tungsten seed material containing the dopant material. A tungsten fill material of lower resistance will then be formed over the tungsten seed material.

Embodiments disclosed herein are directed to forming MOSFET devices. In particular, one or more pre-silicide treatments are performed on a substrate prior to the deposition of the metal-silicide layer to improve the density and performance of the metal-silicide layer in the MOSFETs. The metal-silicide formation formed with the pre-silicide treatment(s) can occur before or after the formation of metal gates during MOSFET fabrication.