An integrated circuit includes an N-type laterally diffused metal-oxide semiconductor (NLDMOS) transistor including an active semiconductor substrate region having P-type conductivity. The integrated circuit further includes a buried semiconductor region having N+-type conductivity underneath the active substrate region. The buried semiconductor region is more heavily doped than the active semiconductor substrate region.

An apparatus includes a drift region formed over the substrate, a body region over the substrate, a first well region formed over the drift region, a collector region formed in the first well region, an emitter region formed in the body region, a first body contact formed in the body region, a first gate situated between the collector region and the emitter region, a second well region formed over the substrate, a drain region formed in the second well region, wherein the drain region and the emitter region are electrically connected to each other, a source region formed in the second well region, wherein the source region and the first body contact are electrically connected to each other, and a second gate situated between the drain region and the source region, wherein the second gate and the first gate are electrically connected to each other.

Embodiments of the disclosure provide a bipolar transistor structure on a semiconductor fin. The semiconductor fin may be on a substrate and may have a first doping type, a length in a first direction, and a width in a second direction perpendicular to the first direction. The semiconductor fin includes a first portion and a second portion adjacent the first portion along the length of the semiconductor fin. The second portion is coupled to a base contact. A dopant concentration of the first portion is less than a dopant concentration of the second portion. An emitter/collector (E/C) material is adjacent the first portion along the width of the semiconductor fin. The E/C material has a second doping type opposite the first doping type. The E/C material is coupled to an E/C contact.

A device includes a MOS transistor and a bipolar transistor at a same first portion of a substrate. The first portion includes a first well doped with a first type forming the channel of the MOS transistor and two first regions doped with a second type opposite to the first type that are arranged in the first well which form the source and drain of the MOS transistor. The first portion further includes: a second well doped with the second type that is arranged laterally with respect to the first well to form the base of the bipolar transistor; a second region doped with the first type that is arranged in the second well to form the emitter of the bipolar transistor; and a third region doped with the first type that is arranged under the second well to form the collector of the bipolar transistor.

A device includes a MOS transistor and a bipolar transistor at a same first portion of a substrate. The first portion includes a first well doped with a first type forming the channel of the MOS transistor and two first regions doped with a second type opposite to the first type that are arranged in the first well which form the source and drain of the MOS transistor. The first portion further includes: a second well doped with the second type that is arranged laterally with respect to the first well to form the base of the bipolar transistor; a second region doped with the first type that is arranged in the second well to form the emitter of the bipolar transistor; and a third region doped with the first type that is arranged under the second well to form the collector of the bipolar transistor.

A substrate made of doped single-crystal silicon has an upper surface. A doped single-crystal silicon layer is formed by epitaxy on top of and in contact with the upper surface of the substrate. Either before or after forming the doped single-crystal silicon layer, and before any other thermal treatment step at a temperature in the range from 600° C. to 900° C., a denuding thermal treatment is applied to the substrate for several hours. This denuding thermal treatment is at a temperature higher than or equal to 1,000° C.

A substrate made of doped single-crystal silicon has an upper surface. A doped single-crystal silicon layer is formed by epitaxy on top of and in contact with the upper surface of the substrate. Either before or after forming the doped single-crystal silicon layer, and before any other thermal treatment step at a temperature in the range from 600° C. to 900° C., a denuding thermal treatment is applied to the substrate for several hours. This denuding thermal treatment is at a temperature higher than or equal to 1,000° C.

A modular guided keeper base, guided keeper assembly, and related method includes a modular guided keeper base that mounts to a die member. The guided keeper base has an integrated stop for guide pin retention. The guided keeper base can also accommodate a variety of bushings within the base. The guided keeper base is attached to a die member using a mounting flange(s). Mounting fasteners pass through the fastener holes in the mounting flanges and are anchored in the die member to securely retain the guided keeper assembly in place. A retainer ring is mounted in an associated groove in the base over the heads of the mounting fasteners to prevent unintentional unfastening of the fasteners from the die member.

A modular guided keeper base, guided keeper assembly, and related method includes a modular guided keeper base that mounts to a die member. The guided keeper base has an integrated stop for guide pin retention. The guided keeper base can also accommodate a variety of bushings within the base. The guided keeper base is attached to a die member using a mounting flange(s). Mounting fasteners pass through the fastener holes in the mounting flanges and are anchored in the die member to securely retain the guided keeper assembly in place. A retainer ring is mounted in an associated groove in the base over the heads of the mounting fasteners to prevent unintentional unfastening of the fasteners from the die member.

Embodiments of the disclosure provide an integrated circuit (IC) structure, including: a p-type substrate, a p-well region within the p-type substrate, and an n-type barrier region between the p-type substrate and the p-well region. The n-type barrier region physically isolates the p-type substrate from the p-well region. A field effect transistor (FET) is positioned above the p-well region, and a buried insulator layer on the upper surface of the p-well region separates the transistor from the p-well region. A first voltage source electrically coupled to the p-well region induces a P-N-P junction across the p-well region, the n-type barrier region, and the p-type substrate.