An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad.

An electrostatic discharge protection circuit and a semiconductor device are provided. The circuit includes: a power source terminal, a ground terminal, and a discharge path. The discharge path includes a clamp transistor and a MOS transistor connected in series and integrated into a same semiconductor substrate with different types. For the MOS transistor, a gate electrode is electrically connected to a substrate terminal; a first electrode is one of a source electrode and a drain electrode; a second electrode is another one of the source electrode and the drain electrode; the first electrode is electrically connected to a gate electrode of the clamp transistor; and the second electrode is electrically connected to the ground terminal. When an electrostatic discharge occurs, the MOS transistor is turned on to form parasitic current between a substrate terminal of the clamp transistor and the second electrode of the MOS transistor.

A semiconductor device includes a substrate including a P-well region, a gate electrode on the substrate, and a first region and a second region formed in the substrate on opposite sides adjacent to the gate electrode, the first region includes a first N-well region in the substrate and a second N-well region, a first impurity region, a second impurity region in the first N-well region, the second region includes a third impurity region in the substrate and a fourth impurity region in the third impurity region, a doping concentration of the second N-well region is greater than a doping concentration of the first N-well region, and a doping concentration of the second impurity region is greater than a doping concentration of the second N-well region.

An electrostatic discharge protection circuit is disclosed. It comprises a stacked drain-ballasted NMOS devices structure and a gate bias circuit. The gate bias circuit includes an inverter, a first gate bias output terminal, and a second gate bias output terminal. The first gate bias output terminal is coupled to a gate of a first one of the drain-ballasted NMOS devices. The second gate bias output terminal runs from an output of the inverter to a gate of a second one of the drain-ballasted NMOS devices.

An ESD protection device includes a deep well having a first conductivity type, a well having the first conductivity type disposed in at least a portion of the deep well, proximate an upper surface of the deep well, and a drain region having a second conductivity type disposed in a portion of the deep well, proximate the upper surface of the deep well. A source structure is disposed in a portion of the well, proximate an upper surface of the well and spaced laterally from the drain region. The source structure includes multiple pairs of stripe regions, each of the stripe regions including a doped region of the first conductivity type and a doped region of the second conductivity type disposed laterally adjacent to one another. A gate is disposed over the well, between the drain region and the source structure, the gate being electrically isolated from the well.

An ESD circuit includes a voltage division circuit, a RC control circuit and a voltage selection circuit. The voltage division circuit is connected between a first power pad and a first node, and generates a first voltage. The RC control circuit is connected between the first power pad and a second power pad, and generates a second voltage and a third voltage. The voltage selection circuit receives the first voltage and the second voltage, and outputs a fourth voltage. The first transistor and the second transistor are serially connected between the first power pad and the second power pad. A gate terminal of the first transistor receives the first voltage. A gate terminal of the second transistor receives the third voltage. The third transistor is connected with the first power pad and an internal circuit. A gate terminal of the third transistor receives the fourth voltage.

A BiMOS-type transistor includes a gate region, a channel under the gate region, a first channel contact region and a second channel contact region. The first channel contact region is electrically coupled to the gate region to receive a first potential. The second channel contact region is electrically coupled to receive a second potential.

A high-density source region is formed along a surface of a semiconductor substrate and is connected to either one of a power source line and ground line. A low-density source region has an exposed surface at a surface of the semiconductor substrate and is in contact with the high-density source region. A high-density drain region is formed along the surface of the semiconductor substrate and is connected to the other one of the power source line and the ground line. A low-density drain region has an exposed surface at the surface of the semiconductor substrate, is in contact with the high-density drain region, and extends to a deeper region from the surface of the semiconductor substrate than does the low-density source region. A gate electrode is connected to either one of the power source line and the ground line.

An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad.

A semiconductor device for enhancing electrostatic discharge (ESD) protection and a layout structure thereof are provided. An ESD protection device and a protected device (300) with a small feature linewidth are located on the same well region. The device (300) with the small feature linewidth is located at a middle portion. The ESD protection device is disposed at both sides of the device (300) with the small feature linewidth.