In an integrated circuit supporting complementary metal oxide semiconductor (CMOS) integrated circuits, latch-up immunity is supported by surrounding a hot n-well with an n-well strap spaced from the hot n-well by a specified distance in accordance with design rules. The n-well strap is positioned between the hot n-well and other n-well or n-type diffusion structures.

An apparatus for suppressing parasitic leakage from I/O pins to substrate in floating rail based ESD protection networks is disclosed. In one embodiment, the apparatus includes an integrated circuit (IC) including a conductor, a pin, a first diode coupled between the pin and the conductor, and a first circuit coupled between the conductor and the pin. The first circuit is configured to selectively couple the pin to the conductor based on a voltage on the pin and a voltage on the conductor.

In a method of manufacturing a semiconductor device, selectively forming a first semiconductor region and a fourth semiconductor region to be away from each other in a surface layer of a first principal surface of a semiconductor substrate at a same impurity implantation and impurity diffusion process, selectively forming a second semiconductor region in the first semiconductor region and selectively forming a fifth semiconductor region in the fourth semiconductor region at a same impurity implantation and impurity diffusion process, and selectively forming a third semiconductor region that penetrates the first semiconductor region in a depth direction and selectively forming a sixth semiconductor region that penetrates the fourth semiconductor region in the depth direction at a same impurity implantation and impurity diffusion process.

Methods, apparatus, systems and articles of manufacture are disclosed that provide an apparatus comprising: a first transistor including a first gate, a first current terminal, and a second current terminal; a second transistor including a second gate, a third current terminal, and a fourth current terminal; the first current terminal coupled to the third current terminal; the first gate coupled to the second gate and the second current terminal; a third transistor including a third gate, a fifth current terminal, and a sixth current terminal, the fifth current terminal coupled to the second current terminal, third gate coupled to a voltage reference node; and a fourth transistor including a fourth gate, a seventh current terminal and an eighth current terminal, the seventh current terminal coupled to the sixth current terminal, the fourth gate coupled to the seventh current terminal and the eighth current terminal coupled to the fourth current terminal.

An ESD protection circuit having a discharging transistor and a body snatching circuit. The discharging transistor is electrically coupled between a first node and a second node. The gate of the discharging transistor is electrically coupled to a driving voltage. The body snatching circuit receives the voltages at the first and second nodes and outputs either the voltage at the first node or the voltage at the second node based on which of these two voltages have a lower value. The output voltage of the body snatching circuit is provided to the body of the discharging transistor.

In an integrated circuit supporting complementary metal oxide semiconductor (CMOS) integrated circuits, latch-up immunity is supported by surrounding a hot n-well with an n-well strap spaced from the hot n-well by a specified distance in accordance with design rules. The n-well strap is positioned between the hot n-well and other n-well or n-type diffusion structures.

The present invention provides a high voltage ESD protection device including a P-type substrate; a first NWELL region located on the left of the upper part of the P-type substrate; an NP contact region located on the upper part of the first NWELL region; an N+ contact region located on the right of the upper part of the P-type substrate apart from the first NWELL region; a P+ contact region tangential to the right side of the N+ contact region; a NTOP layer arranged on the right of the NP contact region inside the first NWELL region. The NP contact region is connected to a metal piece to form a metal anode. The N+ contact region and the P+ contact region are connected by a metal piece to form a metal cathode.

A MOSFET and an electrostatic discharge (ESD) protection device on a common chip includes a MOSFET with a source, a gate, and a drain, and an ESD protection device configured to implement a diode function that is biased to prevent current from flowing through the common chip from the source to the drain.

An apparatus for electrostatic discharge protection. In one embodiment, an integrated circuit (IC) includes a trigger circuit configured to generate a trigger voltage VT in response to an electrostatic discharge (ESD) event. A plurality of metal oxide semiconductor (MOS) transistors are coupled to the trigger circuit. The plurality of MOS transistors are configured to conduct ESD current from a plurality of circuit nodes, respectively, to a ground conductor in response to the trigger circuit generating the trigger voltage VT. A voltage limiter circuit is also included and is configured to limit the trigger voltage VT.

In a described example, an apparatus includes: a first metal oxide semiconductor field effect transistor (MOSFET) coupled between a first input terminal for receiving a supply voltage and an output terminal for coupling to a load, and having a first gate terminal; an enable terminal coupled to the first gate terminal for receiving an enable signal; a first current mirror coupled between the first input terminal and a first terminal of a first series resistor and having an input coupled to the first gate terminal; and a second MOSFET coupled between the first gate terminal and the output terminal, and having a second gate terminal coupled to the first terminal of the first series resistor, the first series resistor having a second terminal coupled to the output terminal.