There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate; a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, wherein the second source/drain layer comprises a first semiconductor material which is stressed; and a gate stack surrounding a periphery of the channel layer.

A semiconductor device, a method of manufacturing the same and an electronic device including the semiconductor device are provided. According to embodiments, the semiconductor device may include a substrate, a first source/drain layer, a channel layer and a second source/drain layer stacked in sequence on the substrate, and a gate stack surrounding a periphery of the channel layer. The channel layer includes a channel region close to its peripheral surface and a body region disposed on an inner side of the channel region.

There are provided a semiconductor device, a method of manufacturing the same, and an electronic device including the device. According to an embodiment, the semiconductor device may include a substrate, and a first device and a second device formed on the substrate. Each of the first device and the second device includes a first source/drain layer, a channel layer and a second source/drain layer stacked on the substrate in sequence, and also a gate stack surrounding a periphery of the channel layer. The channel layer of the first device and the channel layer of the second device are substantially co-planar.

Provided is a semiconductor memory device. The semiconductor memory device includes a peripheral circuit gate pattern on a first substrate, an impurity region in the first substrate and spaced apart from the peripheral circuit gate pattern, a cell array structure on the peripheral circuit gate pattern, a second substrate between the peripheral circuit gate pattern and the cell array structure, and a via that is in contact with the impurity region and disposed between the first substrate and the second substrate. The via electrically connects the first and second substrates to each other.

A complementary metal-oxide-semiconductor (CMOS) circuit includes a bulk semiconductor substrate, a first active region and a second active region, a first type transistor, a first localized isolating layer, a second type transistor, and a second localized isolating layer. The bulk semiconductor substrate has an original semiconductor surface. The first active region and the second active region are formed based on the bulk semiconductor substrate. The first type transistor is formed based on the first active region and has a first doped body. The first localized isolating layer is under the first type transistor and at least isolates the first doped body from the bulk semiconductor substrate. The second type transistor is formed based on the second active region and has a second doped body. The second localized isolating layer is under the second type transistor and at least partially isolates the second doped body from the bulk semiconductor substrate.