A semiconductor device and a method of manufacturing a semiconductor device pertain to a semiconductor device having a channel pattern, wherein the channel pattern includes a pipe channel and vertical channels protruding in a first direction from the pipe channel. The semiconductor device also has interlayer insulating layers disposed over the pipe channel and gate electrodes disposed over the pipe channel, wherein the gate electrodes are alternately stacked with the interlayer insulating layers in the first direction, wherein the stacked interlayer insulating layers and gate electrodes surround the vertical channels, and wherein the gate electrodes include a first conductive pattern and second conductive patterns. The semiconductor device further has an etch stop pattern disposed over the first conductive pattern and under the second conductive patterns.

A semiconductor device includes a first stack structure including first interlayer insulating layers and first conductive patterns alternately stacked on each other in a first direction and a second conductive pattern comprising electrode portions and a connecting portion. The electrode portions of the second conductive pattern are stacked to be spaced apart from each other above the first stack structure. The connecting portion of the second conductive pattern extends in the first direction to intersect the electrode portions and couples the electrode portions. The semiconductor device further includes a vertical channel and a vertical conductive structure that pass through the first stack structure and the electrode portions of the second conductive pattern. The vertical conductive structure is spaced apart from the first stack structure and the second conductive pattern.

Some embodiments include a memory cell having a conductive gate comprising ruthenium. A charge-blocking region is adjacent the conductive gate, a charge-storage region is adjacent the charge-blocking region, a tunneling material is adjacent the charge-storage region, and a channel material is adjacent the tunneling material. Some embodiments include an assembly having a vertical stack of alternating insulative levels and wordline levels. The wordline levels contain conductive wordline material which includes ruthenium. Semiconductor material extends through the stack as a channel structure. Charge-storage regions are between the conductive wordline material and the channel structure. Charge-blocking regions are between the charge-storage regions and the conductive wordline material. Some embodiments include methods of forming integrated assemblies.

A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.

Systems, apparatuses and methods may provide for memory cell technology comprising a control gate, a conductive channel, and a charge storage structure coupled to the control gate and the conductive channel, wherein the charge storage structure includes a polysilicon layer and a metal layer. In one example, the metal layer includes titanium nitride or other high effective work function metal.

A semiconductor device includes a substrate. A gate insulating film is formed on the surface of the substrate. A first gate electrode layer is formed on the gate insulating film. A second gate electrode layer is formed on the first gate electrode layer and electrically connected to the first gate electrode layer. A first contact extends through the second gate electrode layer to reach the first gate electrode layer. First and second impurity layers are formed on opposite sides of the first and second gate electrode layers.

A gate electrode is formed on a semiconductor substrate between an n-type source region and an n-type drain region via a first insulating film. The first insulating film has second and third insulating films adjacent to each other in a plan view and, in a gate length direction of the gate electrode, the second insulating film is located on an n-type source region side, and the third insulating film is located on an n-type drain region side. The second insulating film is thinner than the third insulating film. The third insulating film is made of a laminated film having a first insulating film on the semiconductor substrate, a second insulating film on the first insulating film, and a third insulating film on the second insulating film, and each bandgap of the three insulating films is larger than that of the second insulating film.

A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer is has a value between −1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.

A semiconductor memory device includes a semiconductor substrate a gate structure extending in a vertical direction on the semiconductor device, a plurality of charge trap layers spaced apart from each other in the vertical direction and each having a horizontal cross-section with a first ring shape surrounding the gate structure, a plurality of semiconductor patterns spaced apart from each other in the vertical direction and each having a horizontal cross-section with a second ring shape surrounding the plurality of charge trap layers, a source region and a source line at one end of each of the plurality of semiconductor patterns in a horizontal direction, and a drain region and a drain line at an other end of each of the plurality of semiconductor patterns in the horizontal direction. The gate structure may include a gate insulation layer and a gate electrode layer.

Charge storage and sensing devices having a tunnel diode operable to sense charges stored in a charge storage structure are provided. In some embodiments, a device includes a substrate, a charge storage device on the substrate, and tunnel diode on the substrate adjacent to the charge storage device. The tunnel diode includes a tunnel diode dielectric layer on the substrate, and a tunnel diode electrode on the tunnel diode dielectric layer. A substrate electrode is disposed on the doped region of the substrate, and the tunnel diode electrode is positioned between the charge storage device and the substrate electrode.