The invention relates to a normally-off high-electron-mobility field-effect transistor (1), comprising: a superposition of a first layer of semiconductor material (15) and a second layer of semiconductor material (16) so as form an electron gas layer (17) at the interface between these first and second layers; a trench (5) separating the superposition into first and second domains (51, 52); an insulating element (34) positioned in said trench in order to electrically insulate said first and second domains; a p-doped semiconductor element (33) in contact with the first or the second layer of semiconductor material (16) of the first and second domains (51, 52), and extending continuously between the first and second domains; a gate insulator (32) positioned on the semiconductor element (33); a gate electrode (31) positioned on the gate insulator (32).

A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional “2D” semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.

This normally-off mode polarization super junction GaN-based FET has an undoped GaN layer 11, an Al.sub.xGa.sub.1-xN layer 12, an island-like undoped GaN layer 13, a p-type GaN layer 14 and a p-type In.sub.yGa.sub.1-yN layer 15 which are stacked in order. The FET has a gate electrode 16 on the uppermost layer, a source electrode 17 and a drain electrode 17 on the Al.sub.xGa.sub.1-xN layer 12 and a p-type In.sub.zGa.sub.1-zN layer 19 and a gate electrode 20 which are located beside one end of the undoped GaN layer 13 on the Al.sub.xGa.sub.1-xN layer 12. The gate electrode 20 may be provided on the p-type In.sub.zGa.sub.1-zN layer 19 via a gate insulating film. At a non-operating time, n.sub.0≤n.sub.1<n.sub.2<n.sub.3 is satisfied for the concentration n.sub.0 of the 2DEG 22 formed in the undoped GaN layer 11/the Al.sub.xGa.sub.1-xN layer 12 hetero-interface just below the gate electrode 20, the concentration n.sub.1 of the 2DEG 22 just below the gate electrode 16, the concentration n.sub.2 of the 2DEG 22 in the polarization super junction region and the concentration n.sub.3 of the 2DEG 22 in the part between the polarization super junction region and the drain electrode 18.

A method includes forming a fin over a substrate, forming a dummy gate structure over the fin, forming a first spacer over the dummy gate structure, implanting a first dopant in the fin to form a doped region of the fin adjacent the first spacer, removing the doped region of the fin to form a first recess, wherein the first recess is self-aligned to the doped region, and epitaxially growing a source/drain region in the first recess.

Transistors and methods of forming the same include forming a fin that has an active layer between two sacrificial layers. Material from the two sacrificial layers is etched away in a region of the fin. A gate stack is formed around the active layer in the region. Source and drain regions are formed in contact with the active layer.

Semiconductor devices and methods of forming the same are disclosed. The semiconductor devices may include a substrate including a first region and a second region, which are spaced apart from each other with a device isolation layer interposed therebetween, a first gate electrode and a second gate electrode on the first and second regions, respectively, an insulating separation pattern separating the first gate electrode and the second gate electrode from each other and extending in a second direction that traverses the first direction, a connection structure electrically connecting the first gate electrode to the second gate electrode, and a first signal line electrically connected to the connection structure. The first and second gate electrodes are extended in a first direction and are aligned to each other in the first direction. The first signal line may extend in the second direction and may vertically overlap the insulating separation pattern.

A power semiconductor device includes a termination region having a corner and an element region inside the termination region. An SiC substrate spans the element region and the termination region. An interlayer insulating film has an outer edge in the termination region. A source electrode is in contact with the SiC substrate in the element region, and has an outer edge on the interlayer insulating film in the termination region. An insulating protective film covers the outer edge of the interlayer insulating film and the outer edge of the source electrode, and has an inner edge on the source electrode. At the corner of the termination region, the outer edge of the interlayer insulating film has a radius of curvature R1, and the inner edge of the insulating protective film has a radius of curvature R2. The radius of curvature R2 is greater than the radius of curvature R1.

An SRAM includes three Si pillars. In upper parts of the Si pillars, a first load P-channel, a first driver N-channel, and a first selection N-channel are formed, and in lower parts of the Si pillars, a second load P-channel, a second driver N-channel, and a second selection N-channel are formed. At the same height in the Si pillars, a P+ layer and N+ layers that serve as drains are formed, and these layers are connected to connected gates surrounding the second load P-channel and the second driver N-channel. At the same height in the Si pillars, a P+ layer and N+ layers that serve as drains are formed, and these layers are connected to connected gates surrounding the first load P-channel and the first driver N-channel. Gates surrounding the first and second selection N-channels are connected to a word-line terminal.

A semiconductor device includes a drift region of a first conductivity type in a semiconductor body having a first main surface, and a body region of a second conductivity type between the drift region and the first main surface. Trenches extend into the semiconductor body from the first main surface and pattern the semiconductor body into mesas including a first mesa between first and second trenches, and a second mesa between second and third trenches. An electrode in the first trench is one electrode out of an electrode group of an electrode electrically coupled to a first gate driver output, an electrode electrically coupled to a second gate driver output, and an electrode electrically connected to a first load contact. An electrode in the second trench is another electrode out the electrode group, and an electrode in the third trench is a remaining electrode out of the electrode group.

An electronic device with improved variable resistance characteristics and a method for fabricating the same are provided. In an embodiment of the disclosed technology, a method for forming an electronic device with a semiconductor memory includes forming a crystalized doped layer over a substrate; forming a barrier layer over the doped layer; forming a metal layer over the barrier layer; and reacting the barrier layer with a portion of the metal layer. The electronic device and the method of fabricating the same according to embodiments of the disclosed technology may have improved variable resistance characteristics.