A complementary tunneling field effect transistor and a manufacturing method are disclosed, which includes: a first drain region and a first source region that are disposed on a substrate, where they include a first dopant; a first channel that is disposed on the first drain region and a second channel that is disposed on the first source region; a second source region that is disposed on the first channel and a second drain region that is disposed on the second channel, where they include a second dopant; a first epitaxial layer that is disposed on the first drain region and the second source region, and a second epitaxial layer that is disposed on the second drain region and the first source region; and a first gate stack layer that is disposed on the first epitaxial layer, and a second gate stack layer that is disposed on the second epitaxial layer.

The present disclosure provides a thin film transistor array substrate, a method for manufacturing the same and a display device. The method includes forming, on a substrate, a gate electrode, a common electrode, a gate insulation layer, an active layer and a source-drain metal layer, and forming, on the resultant substrate, a pixel electrode and a passivation layer by one patterning process.

Disclosed is a semiconductor device, including: a first pipe gate; a second pipe gate on the first pipe gate; a stacked structure on the second pipe gate; a first channel layer including a first pipe channel layer positioned within the first pipe gate and first cell channel layers connected to the first pipe channel layer; a second channel layer including a second pipe channel layer positioned within the second pipe gate, and second cell channel layers connected to the second pipe channel layer; and a slit insulating layer passing through the stacked structure and positioned between the adjacent second cell channel layers, wherein the second pipe channel layer has a body portion and a protrusion portion extending below the body portion at a position below the slit insulating layer.

A semiconductor device including: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes agate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor.

In an embodiment, a device includes: a dielectric fin on a substrate; a low-dimensional layer on the dielectric fin, the low-dimensional layer including a source/drain region and a channel region; a source/drain contact on the source/drain region; and a gate structure on the channel region adjacent the source/drain contact, the gate structure having a first width at a top of the gate structure, a second width at a middle of the gate structure, and a third width at a bottom of the gate structure, the second width being less than each of the first width and the third width.

The present invention provides a thin-film transistor in which transistor characteristics such as drain current and threshold voltage are improved, and a method of manufacturing the same. The present invention provides a thin-film transistor provided with a source electrode (108), a drain electrode (109), a semiconductor layer (105), a gate electrode (103), and an insulating layer (104); wherein the semiconductor layer (105) contains a composite metal oxide obtained by adding to a first metal oxide an oxide having an oxygen dissociation energy that is at least 200 kJ/mol greater than the oxygen dissociation energy of the first metal oxide, whereby the amount of oxygen vacancy is controlled; and the insulating layer (104) is provided with an SiO.sub.2 layer, a high-permittivity first layer, and a high-permittivity second layer, whereby the dipoles generated at the boundary between the SiO.sub.2 layer and the high-permittivity layers are used to control the threshold voltage.

Embodiments of the present invention disclose an array substrate comprising: a base substrate, a gate line and a gate electrode located on the base substrate; an insulating layer covering the gate line and the gate electrode; an active layer on the insulating layer, corresponding to the gate electrode; an etch stop layer above the active layer, the etch stop layer including a first via hole and a second via hole located above the active layer; a data line, a source electrode and a drain electrode and a pixel electrode on the etch stop layer, wherein the source electrode is connected with the active layer through the first via hole, wherein the etch stop layer is made of a light-shielding material.

A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

The present application discloses a thin film transistor including an active layer, and a source electrode and a drain electrode on the active layer; each of the source electrode and the drain electrode includes a metal electrode sub-layer, and a diffusion barrier sub-layer made of a material comprising M1O.sub.aN.sub.b, wherein M1 is a single metal or a combination of metals, a≧0, and b>0, between the metal electrode sub-layer and the active layer for preventing diffusion of metal electrode material into the active layer.

The n-type to p-type fin-FET strength ratio in an integrated logic circuit may be tuned by the use of cut regions in the active and dummy gate electrodes. In some examples, separate cut regions for the dummy gate electrodes and the active gate electrode may be used to allow for different lengths of gate pass-active regions resulting in appropriately tuned integrated logic circuits.