A device includes a first Group III-Nitride (III-N) material, a gate electrode above the III-N material, and the gate electrode. The device further includes a tiered field plate, suitable for increasing gate breakdown voltage with minimal parasitics. In the tiered structure, a first plate is on the gate electrode, the first plate having a second sidewall laterally beyond a sidewall of the gate, and above the III-N material by a first distance. A second plate on the first plate has a third sidewall laterally beyond the second sidewall and above the III-N material by a second distance, greater than the first. A source structure and a drain structure are on opposite sides of the gate electrode, where the source and drain structures each include a second III-N material.

The present invention provides a TFT on a polymer substrate and a method for producing the TFT. The TFT is, due to its characteristics, particularly suited for applications as backplane in LCD displays and solar cell devices.

A multi-gate high electron mobility transistor (HEMT) and its methods of formation are disclosed. The multi-gate HEMT includes a substrate and an adhesion layer on top of the substrate. A channel layer is disposed on top of the adhesion layer, and a first gate electrode is disposed on top of the channel layer. The first gate electrode has a first gate dielectric layer in between the first gate electrode and the channel layer. A second gate electrode is embedded within the substrate and beneath the channel layer. The second gate electrode has a second gate dielectric layer completely surrounding the second gate electrode. A pair of source and drain contacts are disposed on opposite sides of the first gate electrode.

A semiconductor device of an embodiment includes a substrate, a first electrode, a second electrode, the first electrode provided between the substrate and the second electrode, the oxide semiconductor layer in contact with the first electrode, an oxide semiconductor layer between the first electrode and the second electrode, the oxide semiconductor layer contains Zn and at least one first element selected from In, Ga, Si, Al, and Sn; a conductive layer between the oxide semiconductor layer and the second electrode, the conductive layer in contact with the second electrode, the conductive layer contains O and at least one second element selected from the group consisting of In, Ga, Si, Al, Sn, Zn, and Ti, a gate electrode; and a gate insulating layer between the oxide semiconductor layer and the gate electrode.

A semiconductor device having electrodes of three or more levels, includes: a semiconductor substrate; an epitaxial layer formed on the semiconductor substrate; a transistor formed on the epitaxial layer; a source electrode formed on the epitaxial layer and electrically connected to a source of the transistor; and a gate drawing electrode formed on the epitaxial layer and electrically connected to a gate of the transistor, wherein the source electrode includes a first source electrode, a second source electrode which is an electrode at a second or higher level on the first source electrode, and a third source electrode which is an electrode at a third or higher level on the second source electrode and above the gate drawing electrode, and the gate drawing electrode is an electrode at a second or higher level on the first source electrode and surrounded with the first, second, and third source electrodes.

A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second layer over the first conductive layer, forming a plurality of active regions by etching the second layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.

An electrostatically formed nanowire transistor, includes a source, a drain, and multiple gates surrounding a doped silicon region. The gates include a top gate, a bottom gate, and side gates. The gates induce a channel in said doped silicon region. The channel has a width which is decreased by negative biasing of the side gates, and a height and vertical position controlled by the top and bottom gates.

A transistor whose channel region includes an oxide semiconductor is used as a pull down transistor. The band gap of the oxide semiconductor is 2.0 eV or more, preferably 2.5 eV or more, more preferably 3.0 eV or more. Thus, hot carrier degradation in the transistor can be suppressed. Accordingly, the circuit size of the semiconductor device including the pull down transistor can be made small. Further, a gate of a pull up transistor is made to be in a floating state by switching of on/off of the transistor whose channel region includes an oxide semiconductor. Note that when the oxide semiconductor is highly purified, the off-state current of the transistor can be 1 aA/μm (1×10.sup.−18 A/μm) or less. Therefore, the drive capability of the semiconductor device can be improved.

A semiconductor device includes: a first bit line extending in a first direction; a first word line extending in a second direction intersecting the first direction; a first transistor located at a first intersection of the first word line and the first bit line, the first transistor being connected to the first word line and the first bit line; a first capacitor electrically connected to the first transistor, the first capacitor being located at a first part of the first intersection; a second capacitor electrically isolated from the first transistor, the second capacitor being located at a second part of the first intersection; and a second transistor electrically connected to the second capacitor, the first capacitor and the second capacitor being located between the first transistor and the second transistor.

A thin film transistor array substrate, a method for manufacturing the same and a liquid crystal panel are provided. The film transistor array substrate has a transparent substrate formed with a gate electrode, a gate insulating layer, a semiconductor layer, an etching stop layer, a source electrode, a drain electrode, and a pixel electrode. Through using the MoTi electrode to replace the conventional ITO electrode in the film transistor array substrate, the PV layer can be simultaneously omitted in the manufacturing process of the film transistor array substrate for reducing one of the masks, lowering the manufacturing costs, and expanding the application of the IGZO structure.