Gallium nitride (GaN) integrated circuit technology with multi-layer epitaxy and layer transfer is described. In an example, an integrated circuit structure includes a first channel structure including a plurality of alternating first channel layers and second channel layers, the first channel layers including gallium and nitrogen, and the second layers including gallium, aluminum and nitrogen. A second channel structure is bonded to the first channel structure. The second channel structure includes a plurality of alternating third channel layers and fourth channel layers, the third channel layers including gallium and nitrogen, and the fourth layers including gallium, aluminum and nitrogen.

The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. The structure includes: an extrinsic base region; an emitter region on a first side of the extrinsic base region; a collector region on a second side of the extrinsic base region; and a gate structure comprising a gate oxide and a gate control in a same channel region as the extrinsic base region.

Gallium nitride (GaN) selective epitaxial windows for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon, the substrate having a top surface. A first trench is in the substrate, the first trench having a first width and a first height. A second trench is in the substrate, the second trench having a second width and a second height. The second width is greater than the first width, and the second height is greater than the first height. A first island is in the first trench, the first island including gallium and nitrogen and having first corner facets at least partially below the top surface of the substrate. A second island is in the second trench, the second island including gallium and nitrogen and having second corner facets at least partially below the top surface of the substrate.

A vertical, fin-based field effect transistor (FinFET) device includes an array of individual FinFET cells. The array includes a plurality of rows and columns of separated fins. Each of the separated fins is in electrical communication with a source contact. The vertical FinFET device also includes one or more rows of first inactive fins disposed on a first set of sides of the array of individual FinFET cells, one or more columns of second inactive fins disposed on a second set of sides of the array of individual FinFET cells, and a gate region surrounding the individual FinFET cells of the array of individual FinFET cells, the first inactive fins, and the second inactive fins.

A method for fabricating a lateral diffusion metal oxide semiconductor (LDMOS) device includes the steps of first forming a first fin-shaped structure and a second fin-shaped structure on a substrate, forming a shallow trench isolation (STI) between the first fin-shaped structure and the second fin-shaped structure, forming a first gate structure on the first fin-shaped structure and a second gate structure on the second fin-shaped structure, forming a source region on the first fin-shaped structure, forming a drain region on the second fin-shaped structure, and forming a contact field plate directly on the STI.

Disclosed herein are single electron transistor (SET) devices, and related methods and devices. In some embodiments, a SET device may include: first and second source/drain (S/D) electrodes; a plurality of islands, disposed between the first and second S/D electrodes; and dielectric material disposed between adjacent ones of the islands, between the first S/D electrode and an adjacent one of the islands, and between the second S/D electrode and an adjacent one of the islands.

An object is to provide a semiconductor device having electrical characteristics such as high withstand voltage, low reverse saturation current, and high on-state current. In particular, an object is to provide a power diode and a rectifier which include non-linear elements. An embodiment of the present invention is a semiconductor device including a first electrode, a gate insulating layer covering the first electrode, an oxide semiconductor layer in contact with the gate insulating layer and overlapping with the first electrode, a pair of second electrodes covering end portions of the oxide semiconductor layer, an insulating layer covering the pair of second electrodes and the oxide semiconductor layer, and a third electrode in contact with the insulating layer and between the pair of second electrodes. The pair of second electrodes are in contact with end surfaces of the oxide semiconductor layer.

Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

A semiconductor device includes a substrate, a channel layer provided on the substrate, a semiconductor layer provided on the channel layer, gate fingers and a gate connection wiring provided on the semiconductor layer, and an insulating film provided between the semiconductor layer and the gate fingers, wherein the gate fingers includes a first gate finger, and a second gate finger closer to the center of the gate fingers in an arrangement direction than the first gate finger, wherein a first distance between a lower surface of the first gate finger in contact with the insulating film and an upper surface of the channel layer in contact with the semiconductor layer is greater than a second distance between a lower surface of the second gate finger in contact with the insulating film and the upper surface of the channel layer in contact with the semiconductor layer.

A semiconductor memory device that may include a substrate, an array of memory cells arranged in rows and columns, bit lines and word lines. The memory cells each may include a pillar-shaped active region extending vertically, which includes source/drain regions at upper and lower ends respectively and a channel region between the source/drain regions. The channel region may include a single-crystalline semiconductor material. The memory cells each may further include a gate stack formed around a periphery of the channel region. Each of the bit lines is located below a corresponding column, and electrically connected to the lower source/drain regions of the respective memory cells in the corresponding column. Each of the word lines is electrically connected to the gate stacks of the respective memory cells in a corresponding row.