A semiconductor structure includes a metal gate structure comprising a gate dielectric layer and a gate electrode, a conductive layer disposed over the metal gate structure, and a contact feature in direct contact with the top portion of the conductive layer, where the conductive layer includes a bottom portion disposed below a top surface of the metal gate structure and a top portion disposed over the top surface of the metal gate structure, and where the top portion laterally extends beyond a sidewall of the bottom portion.

A field effect transistor includes a substrate, a source electrode and a drain electrode on the substrate and apart from each other in a first direction, a plurality of channel layers, a gate insulating film surrounding each of the plurality of channel layers, and a gate electrode surrounding the gate insulating film. Each of the plurality of channel layers has ends contacting the source electrode and the drain electrode. The plurality of channel layers are spaced apart from each other in a second direction away from the substrate. The plurality of channel layers include a 2D semiconductor material.

A method includes simultaneously forming a first dummy gate stack and a second dummy gate stack on a first portion and a second portion of a protruding fin, simultaneously removing a first gate electrode of the first dummy gate stack and a second gate electrode of the second dummy gate stack to form a first trench and a second trench, respectively, forming an etching mask, wherein the etching mask fills the first trench and the second trench, patterning the etching mask to remove the etching mask from the first trench, removing a first dummy gate dielectric of the first dummy gate stack, with the etching mask protecting a second dummy gate dielectric of the second dummy gate stack from being removed, and forming a first replacement gate stack and a second replacement gate stack in the first trench and the second trench, respectively.

A field effect transistor includes a source region and a drain region formed within and/or above openings in a dielectric capping mask layer overlying a semiconductor substrate and a gate electrode. A source-side silicide portion and a drain-side silicide portion are self-aligned to the source region and to the drain region, respectively.

A field effect transistor includes a source region and a drain region formed within and/or above openings in a dielectric capping mask layer overlying a semiconductor substrate and a gate electrode. A source-side silicide portion and a drain-side silicide portion are self-aligned to the source region and to the drain region, respectively.

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a first active region and a second fin active region extruded from a semiconductor substrate; an isolation featured formed in the semiconductor substrate and being interposed between the first and second fin active regions; a dielectric gate disposed on the isolation feature; a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region; a first source/drain feature formed in the first fin active region and interposed between the first gate stack and the dielectric gate; a second source/drain feature formed in the second fin active region and interposed between the second gate stack and the dielectric gate; a contact feature formed in a first inter-level dielectric material layer and landing on the first and second source/drain features and extending over the dielectric gate.

III-Nitride heterostructures with low p-type sheet resistance and III-Nitride heterostructure devices with gate recess and devices including the III-Nitride heterostructures are disclosed.

An electrostatically controlled sensor includes a GaN/AlGaN heterostructure having a 2DEG channel in the GaN layer. Source and drain contacts are electrically coupled to the 2DEG channel through the AlGaN layer. A gate dielectric is formed over the AlGaN layer, and gate electrodes are formed over the gate dielectric, wherein each gate electrode extends substantially entirely between the source and drain contacts, wherein the gate electrodes are separated by one or more gaps (which also extend substantially entirely between the source and drain contacts). Each of the one or more gaps defines a corresponding sensing area between the gate electrodes for receiving an external influence. A bias voltage is applied to the gate electrodes, such that regions of the 2DEG channel below the gate electrodes are completely depleted, and regions of the 2DEG channel below the one or more gaps in the direction from source to drain are partially depleted.

A semiconductor device with an active transistor cell comprising a p-doped first and second base layers, surrounding an n type source region, the device further comprising a plurality of first gate electrodes embedded in trench recesses, has additional fortifying p-doped layers embedding the opposite ends of the trench recesses. The additional fortifying layers do not affect the active cell design in terms of cell pitch i.e., the design rules for transistor cell spacing, or hole drainage between the transistor cells, but reduce the gate-collector parasitic capacitance of the semiconductor, hence leading to optimum low conduction and switching losses. To further reduce the gate-collector capacitance, the trench recesses embedding the first gate electrodes can be formed with thicker insulating layers in regions that do not abut the first base layers, so as not to negatively impact the value of the threshold voltage.

A Metal Oxide Semiconductor (MOS) transistor cell design has multiple trench recesses embedding trench gate electrodes longitudinally extending in a third dimension, with interconnected first base layer, source regions, and a second base layer covering portions of the regions between adjacent trench recesses and longitudinally extending in the same third dimension. When a control voltage greater than a threshold value is applied on the trench gate electrodes, no vertical MOS channels are formable on the trench walls because each of trench recesses abuts at least one source regions and a connected highly doped second base layer. Instead, the charge carriers flow from a singular point within the source region, into a radial MOS channel formed only on the lateral walls of those trench regions abutting the first base layer, but not the higher doped second base layer.