A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region

Nitride semiconductor device includes: a substrate; a first nitride semiconductor layer of a first conductivity above the substrate; a second nitride semiconductor layer of a second conductivity different from the first conductivity, above the first nitride semiconductor layer a first opening penetrating through the second nitride semiconductor layer; an electron transport layer and an electron supply layer disposed along inner surfaces of the first opening, in stated sequence from the substrate-side; a gate electrode above the electron supply layer, covering the first opening; a source electrode connected to the electron supply layer and the electron transport layer, at a position separated from the gate electrode; and a drain electrode on a surface of the substrate opposite to a surface on which the first nitride semiconductor layer is disposed. At least part of the second nitride semiconductor layer is fixed to a potential different from a potential of the source electrode.

High-voltage, gallium-nitride Schottky diodes are described that are capable of withstanding reverse-bias voltages of up to and in excess of 2000 V with reverse current leakage as low as 0.4 microamp/millimeter. A Schottky diode may comprise a lateral geometry having an anode located between two cathodes, where the anode-to-cathode spacing can be less than about 20 microns. A diode may include at least one field plate connected to the anode that extends above and beyond the anode towards the cathodes.

A semiconductor device includes: a substrate; and an n-type layer including a nitride semiconductor formed on the surface of the substrate. In the n-type layer, the concentration of donor impurities (excluding O) is 1×10.sup.15 cm.sup.−3 or more and 1×10.sup.20 cm.sup.−3 or less, the concentration of C impurities is 1×10.sup.16 cm.sup.−3 or less, the concentration of O impurities is 1×10.sup.16 cm.sup.−3 or less, the concentration of Ca impurities is 1×10.sup.16 cm.sup.−3 or less, and the sum total of the concentrations of the C impurities, the O impurities, and the Ca impurities is lower than the concentration of the donor impurities. Such a semiconductor device can be fabricated by using a halogen-free vapor phase epitaxy (HF-VPE) device.

The likelihood of formation of a corner resulting from a recess in a part of an n-type semiconductor layer is reduced at a deeper position than a p-type semiconductor layer. A method of manufacturing a semiconductor device comprises: forming a gallium nitride (GaN) based n-type semiconductor layer containing n-type impurities; forming a groove by forming a first mask on a part of a surface of the n-type semiconductor layer and then etching a part uncovered by the first mask; removing the first mask; forming a gallium nitride (GaN) based p-type semiconductor layer containing p-type impurities on the surface of the n-type semiconductor layer including the groove; etching the p-type semiconductor layer so as to expose the n-type semiconductor layer at least in a range differing from a range in the presence of the groove; and forming a metal electrode contacting the exposed n-type semiconductor layer and the p-type semiconductor layer.

In order to provide a power semiconductor device reducing a leakage current due to a defect layer and having a small fluctuation in a threshold voltage, included are an n-type epitaxial film layer formed on a surface of the single crystal n-type semiconductor substrate and having a concave portion and a convex portion; an insulating film formed on a first region in a top portion of the convex portion; a p-type thin film layer formed on a surface of the insulating film and a surface of the n-type epitaxial film layer to form a pn junction between the p-type thin film layer and the n-type epitaxial film layer; and an anode electrode, at least part of which is formed on a surface of the p-type thin film layer and part of which passes through the p-type thin film layer and the insulating film.

An integrated electronic device includes a first terminal and a second terminal, a Schottky diode having a first threshold voltage and coupled between the first terminal and the second terminal, a derivation component having a second threshold voltage greater than the first threshold voltage and coupled between the first terminal and the second terminal. The derivation component comprises a super-junction.

The present invention discloses a method for preparing a GaN rectifier suitable for operating at an alternating current frequency of 35 GHz: sequentially growing, on a silicon substrate, an N-polar GaN buffer layer, a carbon doped semi-insulated N-polar GaN layer, a non-doped N-polar AlGaN layer, a non-doped N-polar GaN layer and a non-doped N-polar InGaN thin film to obtain a rectifier epitaxial wafer; preparing a pattern groove for a schottky contact electrode on the GaN rectifier epitaxial wafer, and depositing the schottky contact electrode in the groove; preparing a pattern for an ohmic contact electrode, and depositing a device ohmic contact electrode on the surface of the epitaxial wafer; subsequently, depositing a silicon nitride passivation layer at a part where there is no electrode on the surface of the epitaxial wafer, and preparing a surface electrode area; and finally, performing mesa isolation treatment on the GaN rectifier epitaxial wafer. The present invention realizes the preparation of a high-frequency GaN rectifier, and improves the performance stability of a rectifier device operating at a high power.

A double Schottky-barrier diode includes a semi-insulating substrate, a left mesa formed by growth and etching on the semi-insulating substrate, a middle mesa formed by growth and etching on the semi-insulating substrate, a right mesa formed by growth and etching on the semi-insulating substrate, two anode probes and two air-bridge fingers. The two Schottky contacts are closely fabricated on the same mesa (middle mesa) in a back-to-back manner to obtain even symmetric C-V characteristics and odd symmetric I-V characteristics from the device level. The output of a frequency multiplier fabricated using the double Schottky-barrier diode only has odd harmonics, but no even harmonics, which is suitable for the production of high-order frequency multipliers. The cathodes of the two Schottky contacts are connected by the buffer layer without ohmic contact.

High-voltage Schottky diodes are described. The diodes are capable of withstanding reverse-bias voltages of up to and in excess of 2000 V with reverse current leakage as low as 0.4 microamp/millimeter. In one example, a Schottky diode includes a conduction layer, a first layer over the conduction layer, a second layer over the first layer, a first cathode and a second cathode spaced apart and in electrical contact with the conduction layer, and an anode over the second layer between the first cathode and the second cathode. The first cathode and the second cathode can be electrically connected to each other as a cathode of the Schottky diode.