Disclosed are a diode and a manufacturing method thereof. The diode includes: a first substrate, the first substrate being an N-type doped substrate with a doping concentration equal to or greater than 1×10.sup.18 cm.sup.−3; a metal atomic layer located on a first surface of the first substrate; an epitaxial structure located on the metal atomic layer; a first electrode located on the epitaxial structure; and a second electrode located on a second surface, opposite to the first surface, of the first substrate. The diode significantly reduces forward conduction voltage drop.

Disclosed are structures and methods related to metallization of a doped gallium arsenide (GaAs) layer. In some embodiments, such metallization can include a tantalum nitride (TaN) layer formed on the doped GaAs layer, and a metal layer formed on the TaN layer. Such a combination can yield a Schottky diode having a low turn-on voltage, with the metal layer acting as an anode and an electrical contact connected to the doped GaAs layer acting as a cathode. Such a Schottky diode can be utilized in applications such as radio-frequency (RF) power detection, reference-voltage generation using a clamp diode, and photoelectric conversion. In some embodiments, the low turn-on Schottky diode can be fabricated utilizing heterojunction bipolar transistor (HBT) processes.

A manufacturing method for a semiconductor element includes providing a mask including an opening on a surface of a substrate while leaving a step difference in the mask at an upper surface region around the opening, epitaxially growing a semiconductor from the surface exposed through the opening to over the upper surface region around the opening, to produce a semiconductor element including a semiconductor layer including a first surface to which the step difference is transferred, and dry-etching the first surface of the semiconductor layer to transfer the step difference, the first surface being a contact surface with the mask before the dry etching is performed. The mask contains an element that serves as a donor or an acceptor in the semiconductor layer.

A merged-PN-Schottky, MPS, diode includes an N substrate, an N-drift layer, a P-doped region in the drift layer, an ohmic contact on the P-doped region, a plurality of cells within the P-doped region and being portions of the drift layer where the P-doped region is absent, an anode metallization on the ohmic contact and on said cells, to form junction-barrier contacts and Schottky contacts respectively. The P-doped region has a grid-shaped layout separating from one another each cell and defining, together with the cells, an active area of the MPS diode. Each cell has a same geometry among quadrangular, quadrangular with rounded corners and circular; and the ohmic contact extends at the doped region with continuity along the grid-shaped layout.

The present invention provides an epitaxial structure of Ga-face group III nitride, its active device, and the method for fabricating the same. The epitaxial structure of Ga-face AlGaN/GaN comprises a substrate, an i-GaN (C-doped) layer on the substrate, an i-Al(y)GaN buffer layer on the i-GaN (C-doped) layer, an i-GaN channel layer on the i-Al(y)GaN buffer layer, and an i-Al(x)GaN layer on the i-GaN channel layer, where x=0.1˜0.3 and y=0.05˜0.75. By using the p-GaN inverted trapezoidal gate or anode structure in device design, the 2DEG in the epitaxial structure of Ga-face group III nitride below the p-GaN inverted trapezoidal structure will be depleted, and thus fabricating p-GaN gate enhancement-mode (E-mode) AlGaN/GaN high electron mobility transistors (HEMTs), p-GaN anode AlGaN/GaN Schottky barrier diodes (SBDs), or hybrid devices.

A gallium nitride power device, including: a gallium nitride substrate; cathodes; a plurality of gallium nitride protruding structures arranged on the gallium nitride substrate and between the cathodes, a groove is formed between adjacent gallium nitride protruding structures; an electron transport layer, covering a top portion and side surfaces of each of the gallium nitride protruding structures; a gallium nitride layer, arranged on the electron transport layer and filling each of the grooves; a plurality of second conductivity type regions, where each of the second conductivity type regions extends downward from a top portion of the gallium nitride layer into one of the grooves, and the top portion of each of the gallium nitride protruding structures is higher than a bottom portion of each of the second conductivity type regions; and an anode, arranged on the gallium nitride layer and the second conductivity type regions.

A semiconductor device includes: a substrate; and an n-type layer including a nitride semiconductor formed on the surface of the substrate. In the n-type layer, the concentration of donor impurities (excluding O) is 1×10.sup.15 cm.sup.−3 or more and 1×10.sup.20 cm.sup.−3 or less, the concentration of C impurities is 1×10.sup.16 cm.sup.−3 or less, the concentration of O impurities is 1×10.sup.16 cm.sup.−3 or less, the concentration of Ca impurities is 1×10.sup.16 cm.sup.−3 or less, and the sum total of the concentrations of the C impurities, the O impurities, and the Ca impurities is lower than the concentration of the donor impurities. Such a semiconductor device can be fabricated by using a halogen-free vapor phase epitaxy (HF-VPE) device.

A process for manufacturing an integrated circuit (IC) with a through via extending through a group III-V layer to a diode is provided. An etch is performed through the group III-V layer, into a semiconductor substrate underlying the group III-V layer, to form a via opening. A doped region is formed in the semiconductor substrate, through the via opening. Further, the doped region is formed with an opposite doping type as a surrounding region of the semiconductor substrate. The through via is formed in the via opening and in electrical communication with the doped region.

A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

An object is to provide a technique that ensures to reduce a parasitic resistance of a semiconductor device while enhancing a breakdown voltage property of a semiconductor device. A portion of a second semiconductor layer exposed from a first semiconductor layer corresponds to a concave portion of a laminated structure and the first semiconductor layer or an adjacent portion of the first semiconductor layer and a second semiconductor layer corresponds to a convex portion of the laminated structure. A first guard ring of a second conductivity type is arranged on side walls of the convex portion, and in the concave portion, a guard ring of the second conductivity type is not arranged, or a second guard ring of the second conductivity type having a thickness thinner than that of the first guard ring is arranged.