An apparatus includes: a first SCR device having a first source terminal coupled to a signal terminal, a first body terminal coupled to the first source terminal, a first gate terminal coupled to the signal terminal, and a first drain terminal; a second SCR device having a second drain terminal coupled to the first drain terminal, a second gate terminal coupled to a reference voltage terminal; and a second source terminal coupled to the reference voltage terminal. The apparatus also includes: a third SCR device having a third source terminal coupled to the signal terminal, a third gate terminal coupled to the first gate terminal, and a third drain terminal; a first capacitor coupled between the third drain terminal and the second gate terminal; and a second capacitor coupled between the second gate terminal and the reference voltage terminal.

A triac has a vertical structure formed from a silicon substrate having an upper surface side. A main metallization on the upper surface side has a first portion resting on a first region of a first conductivity type formed in a layer of a second conductivity type. A second portion of the main metallization rests on a portion of the layer. A gate metallization on the upper surface side rests on a second region of the first conductivity type formed in the layer in the vicinity of the first region. A porous silicon bar formed in the layer at the upper surface side has a first end in contact with the gate metallization and a second end in contact with the main metallization.

A power semiconductor device includes a semiconductor wafer, a thyristor structure, and a bipolar junction transistor. The thyristor structure includes a first emitter layer of a first conductivity type adjacent the first main side, a first base layer of a second conductivity type, a second base layer of the first conductivity type, a second emitter layer of the second conductivity type, a gate electrode, a first main electrode, and a second main electrode arranged. The bipolar junction transistor includes a base electrode electrically separated from the gate electrode, a third main electrode arranged on the first main side and a fourth main electrode arranged on the second main side. The first main electrode is electrically connected to the third main electrode and the second main electrode is electrically connected to the fourth main electrode.

A method for manufacturing an electronic device includes: providing a semiconductor carrier including first and second vertically integrated electronic structures laterally spaced apart from each other, an electrical connection layer disposed over a first side of the semiconductor carrier and electrically connecting the first and second vertically integrated electronic structures with each other; mounting the semiconductor carrier on a support carrier with the first side of the semiconductor carrier facing the support carrier; thinning the semiconductor carrier from a second side opposite the first side; and removing material of the semiconductor carrier in a separation region between the first and second vertically integrated electronic structures to separate a first semiconductor region of the first vertically integrated electronic structure from a second semiconductor region of the second vertically integrated electronic structure with the first and second vertically integrated electronic structures remaining electrically connected with each other via the electrical connection layer.

The present invention relates to the technical field of the power semiconductor device relates to a reverse conducting insulated gate bipolar transistor (RC-IGBT). The RC-IGBT comprises a P-type region, an N-type emitter region, a P-type body contact region, a dielectric trench, a collector region, and an electrical filed cutting-off region. The beneficial effect of the present invention is that, when compared with traditional RC-IGBT, the IGBT of the present invention can eliminate negative resistance effect and effectively improve the performance of forward and reverse conduction.

Methods, systems, circuits, and devices for power-packet-switching power converters using bidirectional bipolar transistors (B-TRANs) for switching. Four-terminal three-layer B-TRANs provide substantially identical operation in either direction with forward voltages of less than a diode drop. B-TRANs are fully symmetric merged double-base bidirectional bipolar opposite-faced devices which operate under conditions of high non-equilibrium carrier concentration, and which can have surprising synergies when used as bidirectional switches for power-packet-switching power converters. B-TRANs are driven into a state of high carrier concentration, making the on-state voltage drop very low.

An ESD protection structure comprising a thyristor structure. The thyristor structure is formed from a first P-doped section comprising a first P-doped well formed within a first region of a P-doped epitaxial layer, a first N-doped section comprising a deep N-well structure, a second P-doped section comprising a second P-doped well formed within a second region of the epitaxial layer, and a second N-doped section comprising an N-doped contact region formed within a surface of the second P-doped well. The ESD protection structure further comprises a P-doped region formed on an upper surface of the deep N-well structure and forming a part of the second P-doped section of the thyristor structure.

An electronic device can include a bidirectional HEMT. In an aspect, the electronic device can include a pair of switch gate and blocking gate electrodes, wherein the switch gate electrodes are not electrically connected to the blocking gate electrodes, and the first blocking, first switch, second blocking, and second switch gate electrodes are on the same die. In another aspect, the electronic device can include shielding structures having different numbers of laterally extending portions. In a further aspect, the electronic device can include a gate electrode and a shielding structure, wherein a portion of the shielding structure defines an opening overlying the gate electrode.