A semiconductor device includes a first barrier film covering the main surface of the active region and the insulating film layer, the first barrier film having an ohmic contact hole that exposes a contact portion of the ohmic contact formation region within the window of the insulating film layer; a base contact layer filled into the ohmic contact hole and making ohmic contact with the contact portion of the ohmic contact formation region; a second barrier film made of titanium, covering the base contact layer and the first barrier film; and a third barrier film made of titanium oxide and titanium nitride, covering a surface of the second barrier film.

An improved gated thyristor that utilizes less silicon area than IGBT, BIPOLARs or MOSFETs sized for the same application is provided. Embodiments of the inventive thyristor have a lower gate charge, and a lower forward drop for a given current density. Embodiments of the thyristor once triggered have a latch structure that does not have the same Cgd or Ceb capacitor that must be charged from the gate, and therefore the gated thyristor is cheaper to produce, and requires a smaller gate driver, and takes up less space than standard solutions. Embodiments of the inventive thyristor provide a faster turn off speed than the typical >600 ns using a modified MCT structure which results in the improved tail current turn off profile (<250 ns). Additionally, series resistance of the device is reduced without comprising voltage blocking ability is achieved. Finally, a positive only gate drive means is taught as is a method to module the saturation current using the gate terminal.

A semiconductor structure is provided, which includes a semiconductor device, a first conductive layer, and a gate runner. The semiconductor device includes an upper surface, a gate terminal, a source terminal, and a drain terminal. The first conductive layer is deposited on the upper surface and coupled to the source terminal. The gate runner is overlapped with the first conductive layer and coupled to the gate terminal. The gate runner and the first conductive layer are configured to contribute a parasitic capacitance between the gate terminal and the source terminal.

A memory circuit with thyristor includes a plurality of memory cells. Each memory cell of the plurality of memory cells includes an access transistor and a thyristor. The thyristor is coupled to the access transistor. At least one of a gate of the access transistor and a gate of the thyristor has a fin structure.

An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a P+ layer (e.g., a substrate), an N epi layer, a P-well, vertical insulated gates formed in the P-well, and N+ regions between at least some of the gates, so that vertical NPN and PNP transistors are formed. A source/emitter electrode is on top, and a drain/cathode electrode is on the bottom of the substrate. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gates, referenced to the source/emitter electrode. Some of the cells are passive, having gates that are either not connected to the active gates or having gates that are shorted to their associated N+ regions, to customize the input capacitance and lower the saturation current. Other techniques are described to form the passive cells.

An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n epi layer, a p-well, vertical insulated gate electrodes formed in the p-well, and n+ regions between the gate electrodes, so that vertical npn and pnp transistors are formed. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gate electrodes, referenced to the cathode. To speed up the removal of residual electrons in the p-well after the gate electrode voltage is removed, a p+ region is added adjacent the n+ regions, and an n-layer is added below the p+ region. The cathode electrode directly contacts the p+ region and the n+ regions. During turn-off, the p+ region provides holes which recombine with the residual electrons to rapidly terminate the current flow.

A semiconductor structure is provided, which includes a semiconductor device, a first conductive layer, and a gate runner. The semiconductor device includes an upper surface, a gate terminal, a source terminal, and a drain terminal. The first conductive layer is deposited on the upper surface and coupled to the source terminal. The gate runner is overlapped with the first conductive layer and coupled to the gate terminal. The gate runner and the first conductive layer are configured to contribute a parasitic capacitance between the gate terminal and the source terminal.

A high power vertical insulated-gate switch is described that includes an active region, containing a cell array, and a surrounding termination region. The termination region is for at least the purpose of controlling a breakdown voltage and does not contain any switching cells. Assuming the anode is the silicon substrate (p-type), it is desirable to have good hole injection efficiency from the substrate in the active region in the device's on-state. Therefore, the substrate should be highly doped (p++) in the active region. It is desirable to have poor hole injection efficiency in the termination region so that there is a minimum concentration of holes in the termination region when the switch is turned off. Various doping techniques are disclosed that cause the substrate to efficiency inject holes into the active region but inefficiently inject holes into the termination region during the on-state.

Thyristor memory cell arrays and their fabrication have improved features. Assist-gates between thyristor memory cells in an array operate on both sides of an assist-gate. The assist-gates can be arranged in various ways for optimized performance and the materials of the assist-gate are selected to control the bias voltage of the assist-gate in operation. The PNPN (or NPNP) thyristor layers of the memory cell can be fabricated in different process flows according to manufacturing concerns and the dopant concentrations of the layers are selected to reduce temperature sensitivity of the memory cell.

The present disclosure relates to a Dual Fin SCR device having two parallel fins on which cathode, anode, n- and p- type triggering taps are selectively doped, wherein one Fin (or group of parallel Fins) comprises anode and n-tap, and other Fin (or group of parallel Fins) comprises cathode and p-tap. As key regions of the proposed SCR (anode and cathode), which carry majority of current after triggering, are placed diagonally, they provide substantial benefit in terms of spreading current and dissipating heat. The proposed SCR ESD protection device helps obtain regenerative feedback between basecollector junctions of two back-to-back bipolar transistors, which enables the proposed SCR to shunt ESD current. The proposed SCR design enables lower trigger and holding voltage for efficient and robust ESD protection. The proposed SCR device/design helps offer a tunable trigger voltage and a holding voltage with highfailure threshold.