A method includes depositing a first dielectric layer covering an electrical connector, depositing a second dielectric layer over the first dielectric layer, and performing a first etching process to etch-through the second dielectric layer and the first dielectric layer. An opening is formed in the first dielectric layer and the second dielectric layer to reveal the electrical connector. A second etching process is performed to laterally etch the first dielectric layer and the second dielectric layer. An isolation layer is deposited to extend into the opening. The isolation layer has a vertical portion and a first horizontal portion in the opening, and a second horizontal portion overlapping the second dielectric layer. An anisotropic etching process is performed on the isolation layer, with the vertical portion of the isolation layer being left in the opening.

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip; a second interconnection member disposed on the first interconnection member and the semiconductor chip and including redistribution layers electrically connected to the connection pads of the semiconductor chip; a passivation layer disposed on the second interconnection member and having openings exposing at least portions of the redistribution layer of the second interconnection member; and an under-bump metal layer disposed on the passivation layer and filling at least portions of the openings. In the under-bump metal layer, the number of conductor layers formed on a surface of the passivation layer is different from that of conductor layers formed on the exposed redistribution layer and walls of the openings.

A semiconductor device has a conductive via in a first surface of a substrate. A first interconnect structure is formed over the first surface of the substrate. A first bump is formed over the first interconnect structure. The first bump is formed over or offset from the conductive via. An encapsulant is deposited over the first bump and first interconnect structure. A portion of the encapsulant is removed to expose the first bump. A portion of a second surface of the substrate is removed to expose the conductive via. The encapsulant provides structural support and eliminates the need for a separate carrier wafer when thinning the substrate. A second interconnect structure is formed over the second surface of the substrate. A second bump is formed over the first bump. A plurality of semiconductor devices can be stacked and electrically connected through the conductive via.

A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise an interconnection structure, for example a bond wire, at least a portion of which extends into a dielectric layer utilized to mount a plate, and/or that comprise an interconnection structure that extends upward from the semiconductor die at a location that is laterally offset from the plate.

A device includes an interconnect structure, a barrier multi-layer structure, an oxide layer, a pad metal layer, and a passivation layer. The barrier multi-layer structure is over the interconnect structure, the barrier multi-layer structure includes a first metal nitride layer and a second metal nitride layer over the first metal nitride layer. The oxide layer is over the barrier multi-layer structure, in which the oxide layer is an oxide of the second metal nitride layer of the barrier multi-layer structure. The pad metal layer is over the oxide layer. The passivation layer is in contact with the barrier multi-layer structure, the oxide layer, and the pad metal layer.

In order to improve productivity of a semiconductor device, while improving stability of the blocking voltage of the semiconductor device, this semiconductor device is characterized by having a semiconductor element, and a laminated structure having three resin layers, said laminated structure being in a peripheral section surrounding a main electrode on one surface of the semiconductor element. The semiconductor device is also characterized in that the laminated structure has, on the center section side of the semiconductor element, a region where a lower resin layer is in contact with an intermediate resin layer, and a region where the lower resin layer is in contact with an upper resin layer.

In order to form, in a wide band gap semiconductor device, a high field resistant sealing material having a large end portion film thickness, said high field resistant sealing material corresponding to a reduced termination region having a high field intensity, and to improve accuracy and shorten time of manufacturing steps, this semiconductor device is configured as follows. At least a part of a cross-section of a high field resistant sealing material formed close to a termination region at the periphery of a semiconductor chip has a perpendicular shape at a chip outer peripheral end portion, said shape having, on the chip inner end side, a film thickness that is reduced toward the inner side. In a semiconductor device manufacturing method for providing such semiconductor device, the high field resistant sealing material is formed in a semiconductor wafer state, then, heat treatment is performed, and after dicing is performed, a chip is mounted.

Methods, systems, and apparatuses for preventing corrosion between dissimilar bonded metals. The method includes providing a wafer having a plurality of circuits, each of the plurality of circuits having a plurality of bond pads including a first metal; applying a coating onto at least the plurality of bond pads; etching a hole in the coating on each of the plurality of bond pads to provide an exposed portion of the plurality of bond pads; dicing the wafer to separate each of the plurality of circuits; die bonding each of the plurality of circuits to a respective packaging substrate; and performing a bonding process to bond a second, dissimilar metal to the exposed portion of each of the plurality of bond pads such that the second, dissimilar metal encloses the hole in the coating of each of the plurality of bond pads, thereby enclosing the exposed portion.

A process of forming an electronic device including providing a substrate having a first surface and a second surface opposite the first surface; etching the substrate along the first surface to define a trench; forming a via within the trench; applying a tape including an adhesive to the first surface, wherein the adhesive of the tape is spaced apart from the first surface by a distance; and operating on the second surface of the substrate.

A photoelectric conversion device includes a first semiconductor substrate including a photoelectric conversion unit for generating a signal charge in accordance with an incident light, and a second semiconductor substrate including a signal processing unit for processing an electrical signal on the basis of the signal charge generated in the photoelectric conversion unit. The signal processing unit is situated in an orthogonal projection area from the photoelectric conversion unit to the second semiconductor substrate. A multilayer film including a plurality of insulator layers is provided between the first semiconductor substrate and the second semiconductor substrate. The thickness of the second semiconductor substrate is smaller than 500 micrometers. The thickness of the second semiconductor substrate is greater than the distance from the second semiconductor substrate and a light-receiving surface of the first semiconductor substrate.