A Schottky diode is disclosed that includes a silicon carbide substrate, a silicon carbide drift layer, a Schottky contact, and a passivation structure. The silicon carbide drift layer provides an active region and an edge termination region about the active region. The Schottky contact has sides and a top extending between the two sides and includes a Schottky layer over the active region and an anode contact over the Schottky layer. The passivation structure covers the edge termination region, the sides of the Schottky contact, and at least a portion of the top of the Schottky contact. The passivation structure includes a first silicon nitride layer, a silicon dioxide layer over the first silicon nitride layer, and a second silicon nitride layer over the silicon dioxide layer.

A semiconductor device includes a first passivation layer over an interconnect structure. The semiconductor device further includes a first redistribution line (RDL) via extending through an opening in the first passivation layer to electrically connect to the interconnect structure. The first RDL via includes a first conductive material. The semiconductor device further includes an RDL over the first passivation layer and electrically connected to the first RDL via. The RDL comprises a second conductive material different from the first conductive material. The RDL extends beyond the first RDL via in a direction parallel to a top surface of the first passivation layer.

A semiconductor package includes a first semiconductor element, an insulating layer, and a second semiconductor element. The first semiconductor element includes at least one conductive layer and at least one via layer. The insulating layer is positioned above the first semiconductor device and includes at least one through insulator via (TIV) extending from a first side of the insulating layer to a second side of the insulating layer. The at least one TIV has a conductive core including a copper-containing material. The second semiconductor element is positioned above the insulating layer and includes at least one conductive layer and at least one via layer. The at least one TIV couples the at least one via layer of the first semiconductor element to the at least one via layer of the second semiconductor element.

A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise an interconnection structure, for example a bond wire, at least a portion of which extends into a dielectric layer utilized to mount a plate, and/or that comprise an interconnection structure that extends upward from the semiconductor die at a location that is laterally offset from the plate.

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

A power semiconductor device includes a semiconductor body configured to conduct a load current. A load terminal electrically connected with the semiconductor body is configured to couple the load current into and/or out of the semiconductor body. The load terminal includes a metallization having a frontside and a backside. The backside interfaces with a surface of the semiconductor body. The frontside is configured to interface with a wire structure having at least one wire configured to conduct at least a part of the load current. The frontside has a lateral structure formed at least by at least one local elevation of the metallization. The local elevation has a height in an extension direction defined by a distance between the base and top of the local elevation and, in a first lateral direction perpendicular to the extension direction, a base width at the base and a top width at the top.

A semiconductor chip having a pad, a protective element, and an internal circuit for providing a semiconductor chip having a protective circuit with high noise resistance, wherein the semiconductor chip is characterized in that the resistance value of metal wiring on a path reaching the pad and the protective element is higher than the resistance value of the protective element.

A photoelectric conversion device includes a first semiconductor substrate including a photoelectric conversion unit for generating a signal charge in accordance with an incident light, and a second semiconductor substrate including a signal processing unit for processing an electrical signal on the basis of the signal charge generated in the photoelectric conversion unit. The signal processing unit is situated in an orthogonal projection area from the photoelectric conversion unit to the second semiconductor substrate. A multilayer film including a plurality of insulator layers is provided between the first semiconductor substrate and the second semiconductor substrate. The thickness of the second semiconductor substrate is smaller than 500 micrometers. The thickness of the second semiconductor substrate is greater than the distance from the second semiconductor substrate and a light-receiving surface of the first semiconductor substrate.

To improve reliability of a semiconductor device, in a method of manufacturing the semiconductor device, a semiconductor substrate having an insulating film in which an opening that exposes each of a plurality of electrode pads is formed is provided, and a flux member including conductive particles is arranged over each of the electrode pads. Thereafter, a solder ball is arranged over each of the electrode pads via the flux member, and is then heated via the flux member so that the solder ball is bonded to each of the electrode pads. The width of the opening of the insulating film is smaller than the width (diameter) of the solder ball.

The present invention makes it possible to improve the reliability of a semiconductor device. The semiconductor device has, over a semiconductor substrate, a pad electrode formed at the uppermost layer of a plurality of wiring layers, a surface protective film having an opening over the pad electrode, a redistribution line being formed over the surface protective film and having an upper surface and a side surface, a sidewall barrier film comprising an insulating film covering the side surface and exposing the upper surface of the redistribution line, and a cap metallic film covering the upper surface of the redistribution line. Then the upper surface and side surface of the redistribution line are covered with the cap metallic film or the sidewall barrier film and the cap metallic film and the sidewall barrier film have an overlapping section.