Dielectric breakdown is prevented between opposing two semiconductor chips, to improve the reliability of a semiconductor device. A first semiconductor chip has a wiring structure including a plurality of wiring layers, a first coil formed in the wiring structure, and an insulation film formed over the wiring structure. A second semiconductor chip has a wiring structure including a plurality of wiring layers, a second coil formed over the wiring structure, and an insulation film formed over the wiring structure. The first semiconductor chip and the second semiconductor chip are stacked via an insulation sheet with the insulation film of the first semiconductor chip and the insulation film of the second semiconductor chip facing each other. The first coil and the second coil are magnetically coupled with each other. Then, in each of the first and second semiconductor chips, wires and dummy wires are formed at the uppermost-layer wiring layer.

A manufacturing method of a power MOSFET employs a hard mask film over a portion of the wafer surface as a polishing stopper, between two successive polishing steps. After embedded epitaxial growth is performed in a state where a hard mask film for forming trenches is present in at least a scribe region of a wafer, primary polishing is performed by using the hard mask film as a stopper, and secondary polishing is then performed after the hard mask film is removed.

High voltage integrated circuit capacitors are disclosed. In an example arrangement. A capacitor structure includes a semiconductor substrate; a bottom plate having a conductive layer overlying the semiconductor substrate; a capacitor dielectric layer deposited overlying at least a portion of the bottom plate and having a first thickness greater than about 6 um in a first region; a sloped transition region in the capacitor dielectric at an edge of the first region, the sloped transition region having an upper surface with a slope of greater than 5 degrees from a horizontal plane and extending from the first region to a second region of the capacitor dielectric layer having a second thickness lower than the first thickness; and a top plate conductor formed overlying at least a portion of the capacitor dielectric layer in the first region. Methods and additional apparatus arrangements are disclosed.

A semiconductor device includes a semiconductor chip having a semiconductor substrate with chip and boundary regions, and an integrated circuit on the chip region. A center pad is provided on the chip region and on the integrated circuit, and a boundary pad is provided on the boundary region. The semiconductor device further includes a first lower insulating structure having a contact hole exposing the center pad, a second lower insulating structure , at the same vertical level as the first lower insulating structure, and having a first opening exposing the boundary pad to an outside of the first lower insulating structure, a conductive pattern including a contact portion, a conductive line portion, and a bonding pad portion, and an upper insulating structure formed on the first lower insulating structure and the conductive pattern and having a second opening exposing the bonding pad portion to the outside of the semiconductor chip. The first lower insulating structure has a top surface positioned at a higher vertical level than that of the second lower insulating structure.

To prevent cracks of an interlayer insulation film at the time of wire bonding while maintaining adhesion of an aluminum pad electrode and the interlayer insulation film in a semiconductor device in which the aluminum pad electrode and a lead frame are connected with bonding wire by a ball bonding technology. In a bonding pad that is configured to have multiple pad electrodes each with two or more layers, the pad electrodes being electrically connected with one another through vias, the vias are not arranged under an area to which a capillary end of a wire bonder contacts at the time of the wire boding.

Reliability of a semiconductor device is improved. A slope is provided on a side face of an interconnection trench in sectional view in an interconnection width direction of a redistribution layer. The maximum opening width of the interconnection trench in the interconnection width direction is larger than the maximum interconnection width of the redistribution layer in the interconnection width direction, and the interconnection trench is provided so as to encapsulate the redistribution layer in plan view.

To provide a semiconductor device having improved reliability. The semiconductor device is equipped with a first polyimide film, rewirings formed over the first polyimide film, first and second dummy patterns formed over the first polyimide film, a second polyimide film that covers the rewirings and the dummy patterns, and an opening portion that exposes a portion of the rewirings in the second polyimide film. The first dummy pattern is, in plan view, comprised of a closed pattern surrounding the rewirings while having a space therebetween.

A semiconductor chip and/or a semiconductor package including the same are disclosed. The semiconductor chip may include an integrated circuit on a substrate, a center pad electrically connected to the integrated circuit, a lower insulating structure on the center pad and having a contact hole exposing the center pad, the lower insulating structure including a plurality of lower insulating layers sequentially stacked on the substrate, a conductive pattern including a contact portion, a pad portion, a conductive line portion, the contact portion filling the contact hole, the pad portion including a test region and a bonding region, a conductive line portion on the lower insulating structure and connecting the contact portion to the pad portion, and an upper insulating structure on the conductive pattern and having a first opening exposing the pad portion, and the upper insulating structure including an upper insulating layer and a polymer layer.

Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.

An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal that is constituted of a hexagonal crystal and having a first main surface as a device surface facing a c-plane of the SiC monocrystal and has an off angle inclined with respect to the c-plane, a second main surface at a side opposite to the first main surface, and a side surface facing an a-plane of the SiC monocrystal and has an angle less than the off angle with respect to a normal to the first main surface when the normal is 0.