A power device includes a substrate, a drift layer disposed on the substrate, a terminal region and an active region disposed in the drift layer, an electrode layer disposed on the active region, a Schottky contact layer disposed between the electrode layer and the active region, a passivation layer disposed on the drift layer, and an isolation layer disposed between the passivation layer and the electrode layer so that the passivation layer and the electrode layer are at least partially separated from each other. The isolation layer, the electrode layer, and the passivation layer each respectively has a thermal expansion coefficient a, b, c, and a>b>c.

A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise an interconnection structure, for example a bond wire, at least a portion of which extends into a dielectric layer utilized to mount a plate, and/or that comprise an interconnection structure that extends upward from the semiconductor die at a location that is laterally offset from the plate.

In some embodiments, the present disclosure relates to an integrated chip (IC) structure having a conductive blocking structure configured prevent radiation produced by a device within a first die from affecting an image sensing element within a second die. The IC structure has a first IC die with one or more semiconductor devices and a second IC die with an array of image sensing elements. A hybrid bonding interface region is arranged between the first and second IC die. A conductive bonding structure is arranged within the hybrid bonding interface region and is configured to electrically couple the first IC die to the second IC die. A conductive blocking structure is arranged within the hybrid bonding interface region and extends laterally between the one or more semiconductor devices and the array of image sensing elements.

A power semiconductor device includes a semiconductor body configured to conduct a load current. A load terminal electrically connected with the semiconductor body is configured to couple the load current into and/or out of the semiconductor body. The load terminal includes a metallization having a frontside and a backside. The backside interfaces with a surface of the semiconductor body. The frontside is configured to interface with a wire structure having at least one wire configured to conduct at least a part of the load current. The frontside has a lateral structure formed at least by at least one local elevation of the metallization. The local elevation has a height in an extension direction defined by a distance between the base and top of the local elevation and, in a first lateral direction perpendicular to the extension direction, a base width at the base and a top width at the top.

A semiconductor device includes a standardized carrier. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. The semiconductor wafer is singulated through a first portion of the base semiconductor material to separate the semiconductor die. The semiconductor die are disposed over the standardized carrier. A size of the standardized carrier is independent from a size of the semiconductor die. An encapsulant is deposited over the standardized carrier and around the semiconductor die. An interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The semiconductor device is singulated through the encapsulant. Encapsulant remains disposed on a side of the semiconductor die. Alternatively, the semiconductor device is singulated through a second portion of the base semiconductor and through the encapsulant to remove the second portion of the base semiconductor and encapsulant from the side of the semiconductor die.

A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface and an inactive surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip; a passivation layer disposed on the second interconnection member; and an under-bump metal layer including an external connection pad formed on the passivation layer and a plurality of vias connecting the external connection pad and the redistribution layer of the second interconnection member to each other, wherein the first interconnection member includes a redistribution layer electrically connected to the connection pads of the semiconductor chip.

A light-emitting device, a light-emitting assembly and an integrated circuit (IC) flip-chip are provided. The light-emitting device includes the IC flip-chip, a plurality of light-emitting diode (LED) flip-chips and a substrate. The IC flip-chip includes a plurality of flip-chip pads. The LED flip-chips are spaced apart from the IC flip-chip. The substrate carries the IC flip-chip and the LED flip-chips. The LED flip-chips have a plurality of electrodes, and the flip-chip pads of the IC flip-chip and the electrodes of the LED flip-chips are disposed on the substrate by way of soldering. The LED flip-chips are electrically coupled to the IC flip-chip through the substrate.

A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.

A semiconductor device according to an aspect of the present disclosure includes a semiconductor substrate having a first conductivity type and having a principal surface and a back surface, a silicon carbide semiconductor layer having the first conductivity type and disposed on the principal surface, barrier regions having a second conductivity type and disposed within the silicon carbide semiconductor layer, an edge termination region having the second conductivity type and disposed within the silicon carbide semiconductor layer, the edge termination region enclosing the barrier regions, a first electrode disposed on the silicon carbide semiconductor layer, and a second electrode disposed on the back surface, wherein each of the barrier regions has a polygonal boundary with the silicon carbide semiconductor layer, and each of sides of the polygonal boundary has an angle of 0° to 5° inclusive relative to <11-20> direction of crystal orientations of the semiconductor substrate.

A semiconductor device includes a semiconductor substrate having a main surface; a first coil formed on the main surface; a first insulating film formed over the first coil and having a first main surface; a second insulating film formed on the first main surface of the first insulating film and having a second main surface; and a second coil formed on the second main surface of the second insulating film, wherein the first main surface of the first insulating film has a first area on which the second insulating film is formed, and has a second area without the first area in a plan view, and wherein the second insulating film is surrounded with the second area in the plane view.