A semiconductor package includes: a package substrate; a first semiconductor chip disposed over the package substrate and having a center region and an edge region; and a package redistribution layer disposed over the first semiconductor chip, wherein the first semiconductor chip comprises: a lower structure; a redistribution conductive layer disposed over the lower structure and electrically connected to the lower structure, the redistribution conductive layer including a redistribution pad disposed in the center region; and a protective layer covering the lower structure and the redistribution conductive layer, and having an opening exposing the redistribution pad, wherein the package redistribution layer comprises: a package redistribution conductive layer connected to the redistribution pad and extending to the edge region, the package redistribution conductive layer including a package redistribution pad disposed in the edge region, and, wherein, in the edge region, the redistribution conductive layer is omitted.

A semiconductor device has a first area in which first and third semiconductor elements are formed, a second area in which second and fourth semiconductor elements are formed, and a third area located between the first and second areas. On the first to fourth semiconductor elements, a multilayer wiring layer including first and second inductors is formed. A through hole penetrating the semiconductor substrate is formed in the third area, and a first element isolation portion protruding from a front surface side of the semiconductor substrate toward a back surface side of the semiconductor substrate is formed in the through hole. Further, on the back surface side of the semiconductor substrate, the semiconductor substrate in the first area is mounted on the first die pad, and the semiconductor substrate in the second area is mounted on the second die pad.

A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise an interconnection structure, for example a bond wire, at least a portion of which extends into a dielectric layer utilized to mount a plate, and/or that comprise an interconnection structure that extends upward from the semiconductor die at a location that is laterally offset from the plate.

A semiconductor device includes a pad, a diffusion layer, and a melting layer. The pad included by the semiconductor device includes a concave portion on a surface at which solder connection is to be performed. The diffusion layer included by the semiconductor device is disposed at the concave portion and constituted with a metal which remains on the surface of the pad while diffusing into solder upon the solder connection. The melting layer included by the semiconductor device is disposed adjacent to the diffusion layer and constituted with a metal which diffuses and melts into the solder upon the solder connection.

A package structure is provided. The package structure includes a dielectric structure and an antenna structure disposed in the dielectric structure. The package structure also includes a semiconductor device disposed on the dielectric structure and a protective layer surrounding the semiconductor device. The package structure further includes a conductive feature electrically connecting the semiconductor device and the antenna structure. A portion of the antenna structure is between the conductive feature and the dielectric structure.

A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

A power semiconductor device including a first and second die, each including a plurality of conductive contact regions and a passivation region including a number of projecting dielectric regions and a number of windows. Adjacent windows are separated by a corresponding projecting dielectric region with each conductive contact region arranged within a corresponding window. A package of the surface mount type houses the first and second dice. The package includes a first bottom insulation multilayer and a second bottom insulation multilayer carrying, respectively, the first and second dice. A covering metal layer is arranged on top of the first and second dice and includes projecting metal regions extending into the windows to couple electrically with corresponding conductive contact regions. The covering metal layer moreover forms a number of cavities, which are interposed between the projecting metal regions so as to overlie corresponding projecting dielectric regions.

A semiconductor package includes a first chip, a first chip and a molding compound. The first chip has a first via protruding from the first chip. The second chip has a second via protruding from the second chip, wherein a thickness of the first chip is different from a thickness of the second chip. The molding compound encapsulates the first chip, the second chip, the first via and the second via, wherein surfaces of the first via, the second via and the molding compound are substantially coplanar.

An integrated circuit has an isolation capacitor structure that reduces the risk of breakdown from high electric fields at the edge of the top metal plate of the capacitor. The capacitor structure includes a bottom metal plate above a substrate. A first dielectric layer of a first dielectric material is formed between the bottom metal plate and the top metal plate. The capacitor structure also includes a thin narrow ring formed of a second dielectric material located under a portion of the top metal plate. The second dielectric material has a higher dielectric constant than the first dielectric material. The thin narrow ring follows the shape of the edge of the top metal plate with a portion of the ring underneath the top metal plate and a portion outside the edge of the top metal plate to thereby be located at a place of the maximum electric field.

According to one embodiment, a semiconductor device includes a first electrode, a second electrode, and a wire extending between the first electrode and the second electrode. The wire includes a first conductor in contact with the first electrode and the second electrode, and a second conductor that is provided inside the first conductor and has no contact with the first electrode and the second electrode.