A semiconductor package includes a first chip, a first chip and a molding compound. The first chip has a first via protruding from the first chip. The second chip has a second via protruding from the second chip, wherein a thickness of the first chip is different from a thickness of the second chip. The molding compound encapsulates the first chip, the second chip, the first via and the second via, wherein surfaces of the first via, the second via and the molding compound are substantially coplanar.

An SiC semiconductor device includes an SiC semiconductor layer having a first main surface and a second main surface, a gate electrode embedded in a trench with a gate insulating layer, a source region of a first conductivity type formed in a side of the trench in a surface layer portion of the first main surface, a body region of a second conductivity type formed in a region at the second main surface side with respect to the source region in the surface layer portion of the first main surface, a drift region of the first conductivity type formed in a region at the second main surface side in the SiC semiconductor layer, and a contact region of the second conductivity type having an impurity concentration of not more than 1.0×10.sup.20 cm.sup.−3 and formed in the surface layer portion of the first main surface.

A package structure includes at least one integrated circuit component, an insulating encapsulation, and a redistribution structure. The at least one integrated circuit component includes a semiconductor substrate, an interconnection structure disposed on the semiconductor substrate, and signal terminals and power terminals located on and electrically connecting to the interconnection structure. The interconnection structure is located between the semiconductor substrate and the signal terminals and between the semiconductor substrate and the power terminals, and where a size of the signal terminals is less than a size of the power terminals. The insulating encapsulation encapsulates the at least one integrated circuit component. The redistribution structure is located on the insulating encapsulation and electrically connected to the at least one integrated circuit component.

An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal and having a first main surface as a device surface, a second main surface at a side opposite to the first main surface, and a side surface connecting the first main surface and the second main surface, a main surface insulating layer including an insulating material, covering the first main surface of the SiC semiconductor layer, and having an insulating side surface continuous to the side surface of the SiC semiconductor layer, and a boundary modified layer including a first region that is modified to be of a property differing from the SiC monocrystal and a second region that is modified to be of a property differing from the insulating material, and being formed across the side surface of the SiC semiconductor layer and the insulating side surface of the main surface insulating layer.

A semiconductor device includes: a wire including a first conductive member disposed at a semiconductor substrate and a second conductive member disposed at a surface of the first conductive member, the second conductive member having an ionization tendency less than the first conductive member, wherein the first conductive member includes a first surface disposed close to the second conductive member and having a width smaller than a width of a second surface of the first conductive member which is disposed close to the semiconductor substrate, and wherein the second conductive member has a width larger than the width of the first surface of the first conductive member and smaller than the width of the second surface of the first conductive member.

A semiconductor device includes a first lead, a second lead, a control element, an insulating element, and a driver element. The control element and insulating element are mounted on a first pad portion of the first lead, while the driver element on a second pad portion of the second lead. In plan view, the first pad portion has a first edge adjacent to the second pad portion in a first direction and extending in a second direction perpendicular to the first direction. The first edge has first and second ends opposite in the second direction. The second pad portion has a second edge adjacent to the first edge and extending in the second direction. The second edge has third and fourth ends opposite in the second direction. One of the third and fourth end is located between the first and second end in the second direction.

An integrated circuit (IC) includes a substrate having functional circuitry for realizing at least one circuit function configured together with at least one high voltage isolation component including a top metal feature above the substrate. A crack suppressing dielectric structure including at least a crack resistant dielectric layer is on at least a top of the top metal feature. At least one dielectric passivation overcoat (PO) layer is on an outer portion of the top metal feature.

A semiconductor device includes a protected element, an element isolation region, and a first connection section. The protected element is configured including a diode between an anode region and a cathode region, and is arranged in an active layer of a substrate including the active layer formed over a conductive substrate-support with an insulation layer interposed between the active layer and the substrate-support. The element isolation region includes a trench, an insulation body, and a conductor. The trench extends from a surface of the active layer as far as the insulation layer and surrounds a periphery of the diode. The insulation body is arranged on a side wall of the trench. The conductor fills the trench such that the insulation body is interposed between the conductor and the trench. The first connection section electrically connects the cathode region of the diode and the conductor of the element isolation region.

A semiconductor device according to the present invention includes a first conductive-type SiC semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm.

A semiconductor package includes a semiconductor chip and a redistribution layer structure. The redistribution layer structure is arranged to form an antenna transmitter structure and an antenna receiver structure over the semiconductor chip, wherein patterns of the antenna receiver structure are located at different levels of the redistribution layer structure, and at least one pattern of the antenna transmitter structure is at the same level of the topmost patterns of the antenna receiver structure.