Provided is a semiconductor device capable of reducing a mounting area. A semiconductor device (100) includes a semiconductor element (50) and a control element (150) arranged on a front surface (50a) of the semiconductor element (50). The semiconductor element (50) includes a semiconductor substrate (SB) including a first region AR1 and a second region AR2 adjacent to each other, a first MOS transistor (Tr1) provided is the first region (AR1), and a second MOS transistor (Tr2) provided in the second region (AR2). A first drain region (3a) of the first MOS transistor (Tr1) is connected to a second drain region (3b) of the second MOS transistor (Tr2). The control element (150) turns on and off the first MOS transistor (Tr1) and the second MOS transistor (Tr2).

A semiconductor package including a semiconductor die, an encapsulant, an electrical connector, a conductive pad and an inter-dielectric layer is provided. The encapsulant encapsulates the semiconductor die. The electrical connector is disposed over the semiconductor die. The conductive pad contacts the electrical connector and is disposed between the semiconductor die and the electrical connector. The inter-dielectric layer is disposed over the semiconductor die, wherein the inter-dielectric layer comprises an opening, and a portion of the opening is occupied by the conductive pad and the electrical connector.

Disclosed embodiments include a semiconductor chip including a semiconductor substrate having a top surface with a top connection pad disposed therein, and a protection insulation layer comprising an opening therein, the protection insulation layer not covering at least a portion of the top connection pad, on the semiconductor substrate. The protection insulation layer may include: a bottom protection insulation layer, a cover insulation layer comprising a side cover part that covers at least a portion of a side surface of the bottom protection insulation layer and a top cover part disposed apart from the side cover part to cover at least a portion of a top surface of the bottom protection insulation layer. The protection insulation layer may further include a top protection insulation layer on the top cover part.

A semiconductor package includes: a substrate; a first interposer disposed over the substrate; a first chip stack disposed on the substrate on one side of the first interposer, wherein the first chip stack includes a plurality of first semiconductor chips stacked with an offset in a first direction; a second chip stack disposed on the first chip stack, wherein the second chip stack includes a plurality of second semiconductor chips stacked with an offset in a second direction opposite to the first direction; and a third chip stack disposed on the substrate on an other side of the first interposer, wherein the third chip stack includes a plurality of third semiconductor chips stacked with an offset in the second direction.

In certain aspects, a chip includes a pad, and a first passivation layer, wherein a first portion of the first passivation layer extends over a first portion of the pad. The chip also includes a first metal layer between the first portion of the pad and the first portion of the first passivation layer. The chip further includes an under bump metallization (UBM) electrically coupled to a second portion of the pad.

A semiconductor device is provided that includes a dielectric layer, a bond pad, a passivation layer and a planar barrier. The bond pad is positioned in the dielectric layer. The passivation layer is positioned over the dielectric layer and has an opening over the bond pad. The planar barrier is positioned on the bond pad.

A semiconductor device with improved reliability is provided. The semiconductor device is characterized by its embodiments in that sloped portions are formed on connection parts between a pad and a lead-out wiring portion, respectively. This feature suppresses crack formation in a coating area where a part of the pad is covered with a surface protective film.

A semiconductor device with improved reliability is provided. The semiconductor device is characterized by its embodiments in that sloped portions are formed on connection parts between a pad and a lead-out wiring portion, respectively. This feature suppresses crack formation in a coating area where a part of the pad is covered with a surface protective film.

An apparatus relating generally to a substrate is disclosed. In this apparatus, a post extends from the substrate. The post includes a conductor member. An upper portion of the post extends above an upper surface of the substrate. An exterior surface of the post associated with the upper portion is in contact with a dielectric layer. The dielectric layer is disposed on the upper surface of the substrate and adjacent to the post to provide a dielectric collar for the post. An exterior surface of the dielectric collar is in contact with a conductor layer. The conductor layer is disposed adjacent to the dielectric collar to provide a metal collar for the post, where a top surface of each of the conductor member, the dielectric collar and the metal collar have formed thereon a bond structure for interconnection of the metal collar and the conductor member.

A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.