A semiconductor package includes: a substrate; a first interposer disposed over the substrate; a first chip stack disposed on the substrate on one side of the first interposer, wherein the first chip stack includes a plurality of first semiconductor chips stacked with an offset in a first direction; a second chip stack disposed on the first chip stack, wherein the second chip stack includes a plurality of second semiconductor chips stacked with an offset in a second direction opposite to the first direction; and a third chip stack disposed on the substrate on an other side of the first interposer, wherein the third chip stack includes a plurality of third semiconductor chips stacked with an offset in the second direction.

the semiconductor device includes a substrate, a semiconductor element bonded to the substrate, and a sealing resin sealing at least a part of the substrate and the semiconductor element, in which the semiconductor element includes an active region through which a main current flows in an ON state of the semiconductor element, a terminal region surrounding the active region, an anchor film provided on an insulating film of the terminal region, and a protective film covering at least the terminal region including the anchor film, and the anchor film consists of a material different from the insulating film and has a plurality of openings provided discretely.

A semiconductor device comprising: bonding pads formed in the first wiring layer; and first wirings and a second wiring formed in a second wiring layer provided one layer below the first wiring layer. Here, a power supply potential and a reference potential are to be supplied to each first wiring and the second wiring, respectively. Also, in transparent plan view, each of the first wirings is arranged next to each other, and is arranged at a first position of the second wiring layer, that is overlapped with the bonding region of the first bonding pad. Also, in transparent plan view, the second wiring is arranged at a second position of the second wiring layer, that is overlapped with a first region located between the first bonding pad and the second bonding pad. Further, a width of each first wiring is less than a width of the second wiring.

An alignment apparatus according to one embodiment, includes: a first and a second stage; a first and a second detector; a first and a second moving mechanism; and a controller. The first and second stages are configured to respectively hold a first and a second semiconductor substrate on which a first and a second alignment mark are respectively disposed. The first and second moving mechanisms are configured to respectively move the first and second stages relatively to each other. The controller is configured to perform the following (a), (b). (a) The controller control the detectors and the moving mechanisms to cause the first detector to detect the second alignment mark and to cause the second detector to detect the first alignment mark. (b) The controller calculate a position deviation between the substrates in accordance with results of the detections.

An integrated circuit device includes a wiring structure, first and second inter-wiring insulating layers, redistributions patterns and a cover insulating layer. The wiring structure includes wiring layers having a multilayer wiring structure and via plugs. The first inter-wiring insulating layer that surrounds the wiring structure on a substrate. The second inter-wiring insulating layer is on the first inter-wiring insulating layer, and redistribution via plugs are connected to the wiring structure through the second inter-wiring insulating layer. The redistribution patterns includes pad patterns and dummy patterns on the second inter-wiring insulating layer. Each patterns has a thickness greater than a thickness of each wiring layer. The cover insulating layer covers some of the redistribution patterns. The dummy patterns are in the form of lines that extend in a horizontal direction parallel to the substrate.

Various embodiments of the present disclosure are directed towards a semiconductor structure including a bond pad disposed within a semiconductor substrate. The semiconductor substrate has a back-side surface and a front-side surface opposite the back-side surface. An upper surface of the semiconductor substrate is vertically below the back-side surface. The bond pad extends through the semiconductor substrate. The bond pad includes a conductive body over the upper surface of the semiconductor substrate and conductive protrusions extending from above the upper surface to below the front-side surface of the semiconductor substrate. A vertical distance between a top surface of the bond pad and the back-side surface of the semiconductor substrate is less than a height of the conductive protrusions. A first bond pad isolation structure extends through the semiconductor substrate and laterally surrounds the conductive protrusions.

Provided is a semiconductor device including: a semiconductor layer of a first conductivity type provided on the semiconductor substrate; a first main electrode provided on the semiconductor layer; a second main electrode provided on a main surface of the semiconductor substrate, opposite to a side on which the first main electrode is provided; an electric field limiting region of a second conductivity type provided in an outside terminal end region on an outer peripheral side of the semiconductor device, a first protective film covering at least the electric field limiting region; a protective metal film provided on a portion from an outside end edge portion of the first protective film to a front surface of the semiconductor layer; and a second protective film provided covering portions on an end edge portion of the first main electrode, the first protective film, and the protective metal film.

A semiconductor device includes an inverter circuit having a first switching element and a second switching element, a first control circuit, a second control circuit, and a limiting unit. The first switching element is supplied with a power supply voltage. The second switching element includes a first terminal connected to the first switching element, a second terminal connected to ground, and a control terminal. The first control circuit controls the first switching element. The second control circuit controls the second switching element. The limiting unit reduces fluctuation in voltage between the second terminal and the control terminal based on voltage fluctuation at the second terminal of the second switching element.

Integrated circuit devices and method of manufacturing the same are disclosed. An integrated circuit device includes an interconnect structure on a substrate, a passivation layer on the interconnect structure, a plurality of conductive pads on the passivation layer and a through interconnect via (TIV). The interconnect structure includes a plurality of dielectric layers and an interconnect in the plurality of dielectric layers. The plurality of conductive pads includes a first conductive pad electrically connecting the interconnect. The through interconnect via extends through the plurality of dielectric layers and electrically connecting a first conductive layer of the interconnect.

A pad structure is formed on an IC die and includes a first conductive layer, a dielectric layer, a second conductive layer and a passivation layer. The first conductive layer is formed on an upper surface of the IC die and having a hollow portion. The dielectric layer covers the first conductive layer. The second conductive layer is formed on the dielectric layer and electrically connected to the first conductive layer. The passivation layer covers the second conductive layer and has an opening exposing the second conductive layer for receiving a bonding wire.