A semiconductor structure includes providing a substrate including a first surface and a second surface opposite to the first surface. The first surface is a functional surface. The method also includes forming a plastic seal layer on the first surface of the substrate, and performing a thinning-down process on the second surface of the substrate after forming the plastic seal layer. The plastic seal layer provides support for the substrate during the thinning-down process, and thus warping or cracking of the plastic seal layer 240 may be avoided. In addition, the plastic seal layer can also be used as a material for packaging the substrate. Therefore, after the thinning-down process, the plastic seal layer does not need to be removed. As such, the fabrication process is simplified, and the production cost is reduced.

The present disclosure provides a semiconductor package, including a first semiconductor structure, a first bonding dielectric over the first semiconductor structure and surrounding a first bonding metallization structure, a through via over the first bonding dielectric, and a passive device passive device electrically coupled to the through via and the first bonding metallization structure. The present disclosure also provides a method for manufacturing a semiconductor package, including providing a first die, bonding a second die with the first die, wherein the second die partially covers the first die thereby forming a gap over an uncovered portion of the first die, filling the gap over the first die with dielectric, forming a through dielectric via (TDV) in the filled gap, and forming a passive device over the second die and the TDV.

A semiconductor package includes: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the semiconductor chip; and a connection member including a first insulating layer disposed on the active surface of the semiconductor chip, a first redistribution layer disposed on the first insulating layer, first vias penetrating through the first insulating layer and electrically connecting the connection pads and the first redistribution layer to each other, and a first insulating film covering the first insulating layer and the first redistribution layer. The first insulating film includes a silicon based compound.

A semiconductor device includes a substrate, a wiring formed on the substrate, an anti-reflection film of titanium nitride formed on the wiring, and a silicon oxide film formed on the anti-reflection film. A pad portion which exposes the wiring is formed at a place where a first opening portion and a second opening portion overlap with each other. A metal nitride region containing fewer dangling bonds is formed from a metal nitride film containing fewer dangling bonds than in the anti-reflection film in at least a part of one or both of an opposed surface of the anti-reflection film which faces the silicon oxide film above the anti-reflection film, and an exposed surface of the anti-reflection film which is exposed in the second opening portion.

A semiconductor device includes a semiconductor substrate having a chip region and an edge region, a plurality of connection structures provided in a lower insulating layer of the edge region and arranged at first intervals in a first direction, an upper insulating layer covering the connection structures, and a plurality of redistribution pads disposed on the upper insulating layer and connected to the connection structures, respectively. Each of the redistribution pads includes a pad portion provided on the chip region. The pad portions of the redistribution pads are spaced apart from the connection structures by a first distance in a second direction intersecting the first direction when viewed in a plan view.

A semiconductor device according to the present invention includes a first conductive-type SiC semiconductor layer, and a Schottky metal, comprising molybdenum and having a thickness of 10 nm to 150 nm, that contacts the surface of the SiC semiconductor layer. The junction of the SiC semiconductor layer to the Schottky metal has a planar structure, or a structure with recesses and protrusions of equal to or less than 5 nm.

A package and method of making a package is disclosed. In one example, the package includes an electronic chip having at least one pad, an encapsulant at least partially encapsulating the electronic chip, and an electrically conductive contact element extending from the at least one pad and through the encapsulant so as to be exposed with respect to the encapsulant. The electrically conductive contact element comprises a first contact structure made of a first electrically conductive material on the at least one pad and comprises a second contact structure made of a second electrically conductive material and being exposed with respect to the encapsulant. At least one of the at least one pad has at least a surface portion which comprises or is made of the first electrically conductive material.

In a described example, a method for passivating a copper structure includes: passivating a surface of the copper structure with a copper corrosion inhibitor layer; and depositing a protection overcoat layer with a thickness less than 35 m on a surface of the copper corrosion inhibitor layer.

A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise an interconnection structure, for example a bond wire, at least a portion of which extends into a dielectric layer utilized to mount a plate, and/or that comprise an interconnection structure that extends upward from the semiconductor die at a location that is laterally offset from the plate.

In an embodiment, a method includes forming at least one trench in non-device regions of a first surface of a semiconductor wafer, the non-device regions being arranged between component positions, the component positions including device regions and a first metallization structure, applying a first polymer layer to the first surface of a semiconductor wafer such that the trenches and edge regions of the component positions are covered with the first polymer layer and such that at least a portion of the first metallization structure is uncovered by the first polymer layer, removing portions of a second surface of the semiconductor wafer, the second surface opposing the first surface, revealing portions of the first polymer layer in the non-device regions and producing a worked second surface and inserting a separation line through the first polymer layer in the non-device regions to form a plurality of separate semiconductor dies.