An object is to provide technology that enables cost reduction or downsizing of semiconductor packages. The wiring element includes a second substrate, a plurality of first relay pads arranged on a surface of the second substrate opposite to the conductor substrate and connected to each of the control pads of the plurality of semiconductor elements by wires, a plurality of second relay pads arranged on the surface of the second substrate opposite to the conductor substrate, the number thereof being equal to or lower than the number of the plurality of first relay pads, and a plurality of wiring portions arranged on the surfaceof the second substrate opposite to the conductor substrate and selectively connecting the plurality of first relay pads and the plurality of second relay pads.

An integrated circuit structure includes a substrate with a circuit region thereon and a copper interconnect structure disposed on the substrate. The copper interconnect structure includes an uppermost copper layer covered by a dielectric layer. An aluminum pad layer is provided on the dielectric layer. A metal layer is provided on the circuit region and is located between the uppermost copper layer and the aluminum pad layer.

An integrated semiconductor device having a metallic element formed between a capacitor with and a doped region.

A biosensor system package includes: a transistor structure in a semiconductor layer having a front side and a back side, the transistor structure comprising a channel region; a buried oxide (BOX) layer on the back side of the semiconductor layer, wherein the buried oxide layer has an opening on the back side of the channel region, and an interface layer covers the back side over the channel region; a multi-layer interconnect (MLI) structure on the front side of the semiconductor layer, the transistor structure being electrically connected to the MLI structure; and a cap structure attached to the buried oxide layer, the cap structure comprising a microneedle.

An electronic substrate and an electronic device are provided. The electronic substrate includes a base, a conductive electrode, and a first layer. The conductive electrode and the first layer are disposed on the base, the first layer surrounds the conductive electrode and overlaps an edge portion of the conductive electrode. In a cross-sectional view, the first layer is divided into a first part and a second part, the conductive electrode is located between the first part and the second part, and a width of the first part is different from a width of the second part.

In certain aspects, a chip includes a pad, and a first passivation layer, wherein a first portion of the first passivation layer extends over a first portion of the pad. The chip also includes a first metal layer between the first portion of the pad and the first portion of the first passivation layer. The chip further includes an under bump metallization (UBM) electrically coupled to a second portion of the pad.

Provided is a semiconductor module comprising a semiconductor chip, a lead frame including a chip connection portion configured to connect the lead frame to the semiconductor chip, and a bonding member configured to connect the chip connection portion and the semiconductor chip, wherein the semiconductor chip includes a semiconductor substrate, an active portion provided on the semiconductor substrate, and a transverse protective film provided above the active portion and provided to traverse the active portion in a top view, wherein the chip connection portion includes a center portion which covers a center of the transverse protective film in a top view and a first cut-out portion provided from a first end side of the chip connection portion towards the center portion.

A semiconductor device includes a conductive support member, a first semiconductor element, a second semiconductor element, an insulating element, and a sealing resin. The conductive support member includes a first die pad and a second die pad, which are separated from each other in a first direction. The first die pad and the second die pad overlap each other when viewed along the first direction. When viewed along a thickness direction, a peripheral edge of the first die pad has a first near-angle portion including a first end portion in a second direction orthogonal to both the thickness direction and the first direction. The first near-angle portion is separated from the second die pad in the first direction toward the first end portion in the second direction.

A semiconductor device having a first semiconductor section including a first wiring layer at one side thereof; a second semiconductor section including a second wiring layer at one side thereof, the first and second semiconductor sections being secured together with the respective first and second wiring layer sides of the first and second semiconductor sections facing each other; a conductive material extending through the first semiconductor section to the second wiring layer of the second semiconductor section and by means of which the first and second wiring layers are in electrical communication; and an opening, other than the opening for the conductive material, which extends through the first semiconductor section to the second wiring layer.

A semiconductor device has a first semiconductor die with a base material. A covering layer is formed over a surface of the base material. The covering layer can be made of an insulating material or metal. A trench is formed in the surface of the base material. The covering layer extends into the trench to provide the cantilevered protrusion of the covering layer. A portion of the base material is removed by plasma etching to form a cantilevered protrusion extending beyond an edge of the base material. The cantilevered protrusion can be formed by removing the base material to the covering layer, or the cantilevered protrusion can be formed within the base material under the covering layer. A second semiconductor die is disposed partially under the cantilevered protrusion. An interconnect structure is formed between the cantilevered protrusion and second semiconductor die.