An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal and having a first main surface as an element forming surface, a second main surface at a side opposite to the first main surface, and a plurality of side surfaces connecting the first main surface and the second main surface, and a plurality of modified lines formed one layer each at the respective side surfaces of the SiC semiconductor layer and each extending in a band shape along a tangential direction to the first main surface of the SiC semiconductor layer and modified to be of a property differing from the SiC monocrystal.

A semiconductor module includes a laminated substrate including an insulating board and a plurality of circuit boards that are arranged on an upper face of the insulating board, the plurality of circuit boards including first and second circuit boards, a semiconductor element disposed on the first circuit board and including, on an upper face of the semiconductor element, a main electrode, a gate pad, and a gate runner electrically connected to the gate pad, and a first wiring member electrically connecting the main electrode to the second circuit board. The gate runner extends so as to divide the main electrode into a plurality of electrodes including a first main electrode at a first side and a second main electrode at a second side, and the first wiring member is arranged to cross over the gate runner.

A semiconductor device includes a first chip and a second chip bonded to the first chip. The first chip includes: a substrate; a logic circuit disposed on the substrate; and a plurality of first dummy pads that are disposed above the logic circuit, are disposed on a first bonding surface where the first chip is bonded to the second chip, the plurality of first dummy pads not being electrically connected to the logic circuit. The second chip includes a plurality of second dummy pads disposed on the plurality of first dummy pads and a memory cell array provided above the plurality of second dummy pads. A coverage of the first dummy pads on the first bonding surface is different between a first region and a second region, the first region separated from a first end side of the first chip, the second region disposed between the first end side and the first region.

A semiconductor device of an embodiment includes a first chip having a memory cell array, and a second chip having a control circuit. The first chip includes a substrate, a pad, a first structural body, and a second structural body. The substrate is arranged on the side opposite to a joined face of the first chip joined to the second chip, and includes a first face, a second face, and an opening extending from the second face to the first face in a first region. The memory cell array is provided between the first face and the opposed joined face. The pad is provided in the opening. The first structural body is provided between the first face and the joined face, and is electrically connected to the pad. The second structural body is provided between the first face and the joined face in the first region.

An integrated circuit includes a capacitor with a bottom conductive plate and a top conductive plate. A passivation layer is disposed above the top conductive plate. An intermetal dielectric layer is disposed between the bottom conductive plate and the top conductive plate and is formed of a first dielectric material. Shield layers are disposed between the top conductive plate and above the intermetal dielectric layer and extend horizontally to at least past guard rings. The shield layers include a dielectric layer formed of dielectric material having a dielectric constant greater than the material of the intermetal dielectric layer. The shield layers include horizontally offset trenches to stop horizontal flow of current in the shield layers. The offset ensures there is no vertical path from the passivation layer to lower/ground potentials through the shield layers.

A resistance element includes a plurality of resistance chips stacked vertically, each of the plurality of resistance chips including a semiconductor substrate, one or more resistance layers on a field insulating film, a pad forming electrode on electrically connected to the one or more resistance layers, a relay wiring on the interlayer insulating film, laterally separated from the pad forming electrode, electrically connected to another end of at least one of the one or more resistance layers on one end and to a semiconductor substrate on another end, and a back surface electrode at a bottom of the semiconductor substrate, making ohmic contact with the semiconductor substrate, wherein the plurality of resistance chips have the same planar outer shape, and are stacked one over another so as to constitute a resistor as a whole.

An electronic component includes a covered object, an electrode that covers the covered object and has an electrode side wall on the covered object, an inorganic insulating film that has an inner covering portion covering the electrode such as to expose the electrode side wall, and an organic insulating film that covers the electrode side wall.

This application provides a power semiconductor device, which includes: a semiconductor substrate, where the semiconductor substrate is doped with a first-type impurity; an epitaxial layer, that is doped with the first-type impurity, the epitaxial layer is disposed on a surface of the semiconductor substrate, a first doped region doped with a second-type impurity is disposed on a first surface that is of the epitaxial layer and that is away from the semiconductor substrate, and a circumferential edge of the first surface of the epitaxial layer has a scribing region; a first metal layer, disposed on one side that is of the epitaxial layer and that is away from the semiconductor substrate, where the first metal layer is electrically connected to the epitaxial layer; a second metal layer, disposed on one side that is of the epitaxial layer and that is away from the semiconductor substrate; and a passivation layer.

An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal that is constituted of a hexagonal crystal and having a first main surface as a device surface facing a c-plane of the SiC monocrystal and has an off angle inclined with respect to the c-plane, a second main surface at a side opposite to the first main surface, and a side surface facing an a-plane of the SiC monocrystal and has an angle less than the off angle with respect to a normal to the first main surface when the normal is 0°.

A semiconductor device includes: a semiconductor element that includes an element main body having an element main surface and an element back surface facing opposite sides to each other in a thickness direction, and a first electrode arranged on the element main surface; an insulator that has an annular shape overlapping an outer peripheral edge of the first electrode when viewed in the thickness direction and is arranged over the first electrode and the element main surface; a first metal layer arranged over the first electrode and the insulator; and a second metal layer laminated on the first metal layer and overlapping both the first electrode and the insulator when viewed in the thickness direction.