Provided is a semiconductor device that is resistant to the corrosion of titanium nitride forming an anti-reflection film. The semiconductor device includes: a wiring layer which includes a wiring film made of aluminum or an aluminum alloy and formed on a substrate and a titanium nitride film formed on the wiring film; a protection layer which covers a top surface and a side surface of the wiring layer; and a pad portion which penetrates the protection layer and the titanium nitride film, and which exposes the wiring film, the protection layer including a first silicon nitride film, an oxide film, and a second silicon nitride film which are layered in the stated order from the side of the wiring layer.

Provided are a semiconductor device and a semiconductor package including the same. The semiconductor device comprises a semiconductor chip body including a first chip pad on a top surface, a passivation film disposed on the semiconductor chip body and a first redistribution layer that is disposed between the passivation film and the semiconductor chip body with an opening to expose a first chip center pad region at least partially overlapping the first chip pad, a first redistribution center pad region connected to the first chip center pad region, and a first edge pad region spaced apart from the first redistribution center pad region, through the passivation film, wherein a top surface of the first chip center pad region and a top surface of the first redistribution center pad region are not disposed on the same plane.

Semiconductor packages are provided. One of the semiconductor packages includes a first chip, a second chip, a first adhesive layer, a second adhesive layer and a molding layer. The first adhesive layer is disposed on a first surface of the first chip and a second adhesive layer is disposed on a second surface of the second chip, wherein the first adhesive layer and the second adhesive layer have different thickness, and a total thickness of the first chip and the first adhesive layer is substantially equal to a total thickness of the second chip and the second adhesive layer. The molding layer encapsulates the first chip, the second chip, the first adhesive layer and the second adhesive layer.

A method for manufacturing a semiconductor device having an SiC-IGBT and an SiC-MOSFET in a single semiconductor chip, including forming a second conductive-type SiC base layer on a substrate, and selectively implanting first and second conductive-type impurities into surfaces of the substrate and base layer to form a collector region, a channel region in a surficial portion of the SiC base layer, and an emitter region in a surficial portion of the channel region, the emitter region serving also as a source region of the SiC-MOSFET.

Package structures and methods for forming the same are provided. A package structure includes a semiconductor die. The semiconductor die includes a passivation layer over a semiconductor substrate. The semiconductor die also includes a conductive pad in the passivation layer. The passivation layer partially exposes a top surface of the conductive pad. The package structure also includes an encapsulation layer surrounding the semiconductor die. The package structure further includes a dielectric layer covering the semiconductor die and the encapsulation layer. In addition, the package structure includes a redistribution layer covering the dielectric layer. The redistribution layer extends in the dielectric layer to be physically connected to the top surface of the conductive pad.

A semiconductor device includes a substrate, a contact pad arranged in the substrate, a bump arranged on the contact pad to be electrically connected with the contact pad, an insulating film arranged on the substrate to surround a side surface of the bump and to expose at least a portion of the contact pad to the bump, and a photosensitive film which is formed on the insulating film and comprises a polyimide, wherein the photosensitive film comprises a first region surrounding the side surface of the bump and having a first thickness measured in a vertical direction, and a second region arranged on the first region and having a second thickness thickermeasured in the vertical direction, wherein the second region is spaced apart from the bump in a horizontal direction, and wherein the second thickness is greater than a thickness two times thicker than a difference value between the second thickness and the first thickness.

A method of forming a passivation layer on an integrated circuit (IC) chip including a device layer on a substrate. The method may include forming a crosslinked precursor passivation layer on the IC chip, and curing the crosslinked precursor passivation layer at a first temperature to form a passivation layer. The method may further include maintaining the device layer at a second, lower temperature during the curing of the crosslinked precursor passivation layer. Maintaining the device layer at the second, lower temperature may mitigate and/or prevent damage to the device layer conventionally caused by exposure to the first temperature during the curing of the crosslinked precursor passivation layer. The method may include using a curing system including a chamber, an infrared source for controlling the first temperature for curing the crosslinked precursor passivation layer, and a temperature control device for controlling the second, lower temperature of the device layer.

A semiconductor device with improved reliability is provided. The semiconductor device is characterized by its embodiments in that sloped portions are formed on connection parts between a pad and a lead-out wiring portion, respectively. This feature suppresses crack formation in a coating area where a part of the pad is covered with a surface protective film.

An integrated fan-out package includes a die, an encapsulant, a redistribution structure, a seed layer, conductive pillars, and a buffer layer. The encapsulant encapsulates the die. The redistribution structure is over the die and the encapsulant. The redistribution structure includes dielectric layers and conductive patterns. The dielectric layers are sequentially stacked and the conductive patterns are sandwiched between the dielectric layers. The seed layer and the conductive pillars are sequentially stacked over the redistribution structure. The seed layer is directly in contact with the conductive patterns closest to the conductive pillars. The buffer layer is disposed over the redistribution structure. The dielectric layer closest to the conductive pillars and the buffer layer are sandwiched between the seed layer and the conductive patterns closest to the conductive pillars. A Young's modulus of the buffer layer is higher than a Young's modulus of each of the dielectric layers of the redistribution structure.

A semiconductor device includes: a wire including a first conductive member disposed at a semiconductor substrate and a second conductive member disposed at a surface of the first conductive member, the second conductive member having an ionization tendency less than the first conductive member, wherein the first conductive member includes a first surface disposed close to the second conductive member and having a width smaller than a width of a second surface of the first conductive member which is disposed close to the semiconductor substrate, and wherein the second conductive member has a width larger than the width of the first surface of the first conductive member and smaller than the width of the second surface of the first conductive member.