In an embodiment, a method includes forming at least one trench in non-device regions of a first surface of a semiconductor wafer, the non-device regions being arranged between component positions, the component positions including device regions and a first metallization structure, applying a first polymer layer to the first surface of a semiconductor wafer such that the trenches and edge regions of the component positions are covered with the first polymer layer and such that at least a portion of the first metallization structure is uncovered by the first polymer layer, removing portions of a second surface of the semiconductor wafer, the second surface opposing the first surface, revealing portions of the first polymer layer in the non-device regions and producing a worked second surface and inserting a separation line through the first polymer layer in the non-device regions to form a plurality of separate semiconductor dies.

A semiconductor die includes a last metallization layer above a semiconductor substrate, a bond pad above the last metallization layer, a passivation layer covering part of the bond pad and having an opening that defines a contact area of the bond pad, an insulating region separating the bond pad from the last metallization layer at least in an area corresponding to the contact area of the bond pad, and an electrically conductive interconnection structure that extends from the bond pad to the upper metallization layer outside the contact area of the bond pad. Corresponding methods of manufacture are also provided.

A semiconductor device includes: a conductive structure, a conductive bump extending into the conductive structure and contacting the conductive structure along a first surface, the conductive bump configured to interface with an external semiconductor device at a second surface opposite the first surface, the conductive bump being wider along the first surface than the second surface.

The manufacturing method of a semiconductor device can improve the mechanical strength of a pad more than before, and suppress the occurrence of a crack. The manufacturing method of a semiconductor device includes: forming a first pad constituted by a first metal layer; forming an insulating layer on the first pad; providing an opening portion in the insulating layer by removing the insulating layer on at least a partial region of the first pad; forming a second pad constituted by a second metal layer in the opening portion of the insulating layer so as to have a film thickness that is smaller than the film thickness of the insulating layer; and forming a third pad constituted by a third metal layer on the second pad.

Implementations of a method of forming semiconductor packages may include: providing a wafer having a plurality of devices, etching one or more trenches on a first side of the wafer between each of the plurality of devices, applying a molding compound to the first side of the wafer to fill the one or more trenches; grinding a second side of the wafer to a desired thickness, and exposing the molding compound included in the one or more trenches. The method may include etching the second side of the wafer to expose a height of the molding compound forming one or more steps extending from the wafer, applying a back metallization to a second side of the wafer, and singulating the wafer at the one or more steps to form a plurality of semiconductor packages. The one or more steps may extend from a base of the back metallization.

A semiconductor device includes a first chip and a second chip bonded to the first chip. The first chip includes: a substrate; a logic circuit disposed on the substrate; and a plurality of first dummy pads that are disposed above the logic circuit, are disposed on a first bonding surface where the first chip is bonded to the second chip, the plurality of first dummy pads not being electrically connected to the logic circuit. The second chip includes a plurality of second dummy pads disposed on the plurality of first dummy pads and a memory cell array provided above the plurality of second dummy pads. A coverage of the first dummy pads on the first bonding surface is different between a first region and a second region, the first region separated from a first end side of the first chip, the second region disposed between the first end side and the first region.

A stacked via structure including a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer and a second conductive via is provided. The first dielectric layer includes a first via opening. The first conductive via is in the first via opening. A first level height offset is between a top surface of the first conductive via and a top surface of the first dielectric layer. The first redistribution wiring covers the top surface of the first conductive via and the top surface of the first dielectric layer. The second dielectric layer is disposed on the first dielectric layer and the first redistribution wiring. The second dielectric layer includes a second via opening. The second conductive via is in the second via opening. The second conductive via is electrically connected to the first redistribution wiring through the second via opening of the second dielectric layer.

A method is provided. The method includes forming an interconnect structure electrically connected to a semiconductor device; forming a tantalum-based barrier layer over the interconnect structure; oxidizing the tantalum-based barrier layer to form a tantalum oxide over the tantalum-based barrier layer; and forming a metal layer over the tantalum oxide.

Apparatus and associated methods relate to a bond-pad structure having small pad-substrate capacitance for use in high-voltage MOSFETs. The bond-pad structure includes upper and lower polysilicon plates interposed between a metal bonding pad and an underlying semiconductor substrate. The lower polysilicon plate is encapsulated in dielectric materials, thereby rendering it floating. The upper polysilicon plate is conductively coupled to a source of the high-voltage MOSFET. A perimeter of the metal bonding pad is substantially circumscribed, as viewed from a plan view perspective, by a perimeter of the upper polysilicon plate. A perimeter of the upper polysilicon plate is substantially circumscribed, as viewed from the plan view perspective, by a perimeter of the lower polysilicon plate. In some embodiments, the metal bonding pad is conductively coupled to a gate of the high-voltage MOSFET. The pad-substrate capacitance is advantageously made small by this bond-pad structure.

A semiconductor device according to an exemplary embodiment includes a semiconductor substrate, an interlayer insulating layer, at least one electrode, an inorganic protective layer, and an organic protective layer. The interlayer insulating layer is formed on the semiconductor substrate and has at least one opening. The at least one electrode has part formed on an edge of the at least one opening, and has other part electrically connected, in the at least one opening, to the semiconductor substrate. The inorganic protective layer includes an inner edge portion and an outer edge portion. The inner edge portion covers an edge of the at least one electrode. The inorganic protective layer, except for the inner edge portion, is formed on the interlayer insulating layer. The organic protective layer covers the inorganic protective layer. One of the inner edge portion and the outer edge portion of the inorganic protective layer has an undercut.